Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network

This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (I...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Murgai, R., Shibuya, T., Ito, N., Chung-Kuan Cheng
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Clocks Helium Integer linear programming Laboratories Logic Network-on-a-chip Packaging Very large scale integration Voltage
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