Optimal Margin Computation for At-Speed Test

In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called test ma...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jinjun Xiong, Zolotov, V., Visweswariah, C., Habitz, P.A.
Format:	Tagungsbericht
Sprache:	eng ; jpn
Schlagworte:	Aging Circuit testing Delay Face detection Frequency Manufacturing processes Semiconductor device modeling Temperature Timing Voltage
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!