Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
We present low power illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modify...
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creator | Chandra, A. Ng, F. Kapur, R. |
description | We present low power illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture is independent of the ATPG patterns and imposes a very small combinational area penalty due to the logic added between the scan cells and the CUT. Experimental results for two industrial circuits show that we can simultaneously achieve up to 47% reduction in dynamic power dissipation due to switching and 10X test data volume reduction with LPILS over basic scan. |
doi_str_mv | 10.1109/DATE.2008.4484724 |
format | Conference Proceeding |
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By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture is independent of the ATPG patterns and imposes a very small combinational area penalty due to the logic added between the scan cells and the CUT. Experimental results for two industrial circuits show that we can simultaneously achieve up to 47% reduction in dynamic power dissipation due to switching and 10X test data volume reduction with LPILS over basic scan.</description><identifier>ISSN: 1530-1591</identifier><identifier>ISBN: 3981080130</identifier><identifier>ISBN: 9783981080131</identifier><identifier>EISSN: 1558-1101</identifier><identifier>EISBN: 3981080149</identifier><identifier>EISBN: 9783981080148</identifier><identifier>DOI: 10.1109/DATE.2008.4484724</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic test pattern generation ; Broadcasting ; Built-in self-test ; Circuit testing ; Energy consumption ; Integrated circuit testing ; Logic testing ; Power dissipation ; Switching circuits ; Transistors</subject><ispartof>2008 Design, Automation and Test in Europe, 2008, p.462-467</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4484724$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4484724$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chandra, A.</creatorcontrib><creatorcontrib>Ng, F.</creatorcontrib><creatorcontrib>Kapur, R.</creatorcontrib><title>Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction</title><title>2008 Design, Automation and Test in Europe</title><addtitle>DATE</addtitle><description>We present low power illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture is independent of the ATPG patterns and imposes a very small combinational area penalty due to the logic added between the scan cells and the CUT. Experimental results for two industrial circuits show that we can simultaneously achieve up to 47% reduction in dynamic power dissipation due to switching and 10X test data volume reduction with LPILS over basic scan.</description><subject>Automatic test pattern generation</subject><subject>Broadcasting</subject><subject>Built-in self-test</subject><subject>Circuit testing</subject><subject>Energy consumption</subject><subject>Integrated circuit testing</subject><subject>Logic testing</subject><subject>Power dissipation</subject><subject>Switching circuits</subject><subject>Transistors</subject><issn>1530-1591</issn><issn>1558-1101</issn><isbn>3981080130</isbn><isbn>9783981080131</isbn><isbn>3981080149</isbn><isbn>9783981080148</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkE1LAzEYhOMX2FZ_gHjJH9j65muTHEutWigodvHgpWSTtxjZbmQ3S_HfW7HgaQ7PzMAMITcMpoyBvbufVYspBzBTKY3UXJ6QsbCGgQEm7SkZMaVMcbCys38g4PwXCCiYsuySjPv-EwCU4HZE3ldpT1_SHju6bJrYptjTtXctnXX-I2b0eeiQblNH13E3NNm1mIb-mHBtoBX2md677OhbaoYd0lcMg88xtVfkYuuaHq-POiHVw6KaPxWr58flfLYqooVcGGVKjxqVsKEUdRn0YVngSjOOXJcGbOCClaH2vGbaCQXaG-lrJ7V39daLCbn9q42IuPnq4s5135vjP-IHZrRVlA</recordid><startdate>200803</startdate><enddate>200803</enddate><creator>Chandra, A.</creator><creator>Ng, F.</creator><creator>Kapur, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200803</creationdate><title>Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction</title><author>Chandra, A. ; Ng, F. ; Kapur, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-8586ce7e539d63b6d7484d25712e276809d2316dbc2b17a3507c84cba47cabfc3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Automatic test pattern generation</topic><topic>Broadcasting</topic><topic>Built-in self-test</topic><topic>Circuit testing</topic><topic>Energy consumption</topic><topic>Integrated circuit testing</topic><topic>Logic testing</topic><topic>Power dissipation</topic><topic>Switching circuits</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Chandra, A.</creatorcontrib><creatorcontrib>Ng, F.</creatorcontrib><creatorcontrib>Kapur, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chandra, A.</au><au>Ng, F.</au><au>Kapur, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction</atitle><btitle>2008 Design, Automation and Test in Europe</btitle><stitle>DATE</stitle><date>2008-03</date><risdate>2008</risdate><spage>462</spage><epage>467</epage><pages>462-467</pages><issn>1530-1591</issn><eissn>1558-1101</eissn><isbn>3981080130</isbn><isbn>9783981080131</isbn><eisbn>3981080149</eisbn><eisbn>9783981080148</eisbn><abstract>We present low power illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynamic power dissipation during scan testing in registers and combinational cells can be significantly reduced without modifying the clock tree of the design. The proposed architecture is independent of the ATPG patterns and imposes a very small combinational area penalty due to the logic added between the scan cells and the CUT. Experimental results for two industrial circuits show that we can simultaneously achieve up to 47% reduction in dynamic power dissipation due to switching and 10X test data volume reduction with LPILS over basic scan.</abstract><pub>IEEE</pub><doi>10.1109/DATE.2008.4484724</doi><tpages>6</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Automatic test pattern generation Broadcasting Built-in self-test Circuit testing Energy consumption Integrated circuit testing Logic testing Power dissipation Switching circuits Transistors |
title | Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction |
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