Performance Analysis of SoC Architectures Based on Latency-Rate Servers

This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly cap...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Vink, J.P., van Berkel, K., van der Wolf, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 205
container_issue
container_start_page 200
container_title
container_volume
creator Vink, J.P.
van Berkel, K.
van der Wolf, P.
description This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.
doi_str_mv 10.1109/DATE.2008.4484686
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4484686</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4484686</ieee_id><sourcerecordid>4484686</sourcerecordid><originalsourceid>FETCH-LOGICAL-i1336-632ec67dfc6cb50d2a308512e87104bd77721e1c1ae72bd08ec21f6b07cb5fce3</originalsourceid><addsrcrecordid>eNpFkM1Kw0AURsc_sK0-gLiZF0i8dyaZmSxjWqsQUGxdl8nkBiNtIjNRyNsbseDqLM7hW3yM3SDEiJDdLfPtKhYAJk4SkyijTthcZgbBACbZKZthmppoSvHsX0g4_xUSIkwzvGTzED4AIJUim7H1C_mm9wfbOeJ5Z_djaAPvG77pC557994O5IYvT4Hf20A17zte2oE6N0avE_mG_Df5cMUuGrsPdH3kgr09rLbFY1Q-r5-KvIxalFJFSgpySteNU65KoRZWgklRkNEISVVrrQUSOrSkRVWDISewURXoKW8cyQW7_dttiWj36duD9ePu-Ib8AZ2CTvs</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Performance Analysis of SoC Architectures Based on Latency-Rate Servers</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Vink, J.P. ; van Berkel, K. ; van der Wolf, P.</creator><creatorcontrib>Vink, J.P. ; van Berkel, K. ; van der Wolf, P.</creatorcontrib><description>This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.</description><identifier>ISSN: 1530-1591</identifier><identifier>ISBN: 3981080130</identifier><identifier>ISBN: 9783981080131</identifier><identifier>EISSN: 1558-1101</identifier><identifier>EISBN: 3981080149</identifier><identifier>EISBN: 9783981080148</identifier><identifier>DOI: 10.1109/DATE.2008.4484686</identifier><language>eng</language><publisher>IEEE</publisher><subject>Calculus ; Delay ; Digital video broadcasting ; Heart ; Network servers ; Performance analysis ; Power system interconnection ; Telecommunication traffic ; Traffic control ; Upper bound</subject><ispartof>2008 Design, Automation and Test in Europe, 2008, p.200-205</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4484686$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4484686$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Vink, J.P.</creatorcontrib><creatorcontrib>van Berkel, K.</creatorcontrib><creatorcontrib>van der Wolf, P.</creatorcontrib><title>Performance Analysis of SoC Architectures Based on Latency-Rate Servers</title><title>2008 Design, Automation and Test in Europe</title><addtitle>DATE</addtitle><description>This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.</description><subject>Calculus</subject><subject>Delay</subject><subject>Digital video broadcasting</subject><subject>Heart</subject><subject>Network servers</subject><subject>Performance analysis</subject><subject>Power system interconnection</subject><subject>Telecommunication traffic</subject><subject>Traffic control</subject><subject>Upper bound</subject><issn>1530-1591</issn><issn>1558-1101</issn><isbn>3981080130</isbn><isbn>9783981080131</isbn><isbn>3981080149</isbn><isbn>9783981080148</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1Kw0AURsc_sK0-gLiZF0i8dyaZmSxjWqsQUGxdl8nkBiNtIjNRyNsbseDqLM7hW3yM3SDEiJDdLfPtKhYAJk4SkyijTthcZgbBACbZKZthmppoSvHsX0g4_xUSIkwzvGTzED4AIJUim7H1C_mm9wfbOeJ5Z_djaAPvG77pC557994O5IYvT4Hf20A17zte2oE6N0avE_mG_Df5cMUuGrsPdH3kgr09rLbFY1Q-r5-KvIxalFJFSgpySteNU65KoRZWgklRkNEISVVrrQUSOrSkRVWDISewURXoKW8cyQW7_dttiWj36duD9ePu-Ib8AZ2CTvs</recordid><startdate>200803</startdate><enddate>200803</enddate><creator>Vink, J.P.</creator><creator>van Berkel, K.</creator><creator>van der Wolf, P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200803</creationdate><title>Performance Analysis of SoC Architectures Based on Latency-Rate Servers</title><author>Vink, J.P. ; van Berkel, K. ; van der Wolf, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1336-632ec67dfc6cb50d2a308512e87104bd77721e1c1ae72bd08ec21f6b07cb5fce3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Calculus</topic><topic>Delay</topic><topic>Digital video broadcasting</topic><topic>Heart</topic><topic>Network servers</topic><topic>Performance analysis</topic><topic>Power system interconnection</topic><topic>Telecommunication traffic</topic><topic>Traffic control</topic><topic>Upper bound</topic><toplevel>online_resources</toplevel><creatorcontrib>Vink, J.P.</creatorcontrib><creatorcontrib>van Berkel, K.</creatorcontrib><creatorcontrib>van der Wolf, P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vink, J.P.</au><au>van Berkel, K.</au><au>van der Wolf, P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Performance Analysis of SoC Architectures Based on Latency-Rate Servers</atitle><btitle>2008 Design, Automation and Test in Europe</btitle><stitle>DATE</stitle><date>2008-03</date><risdate>2008</risdate><spage>200</spage><epage>205</epage><pages>200-205</pages><issn>1530-1591</issn><eissn>1558-1101</eissn><isbn>3981080130</isbn><isbn>9783981080131</isbn><eisbn>3981080149</eisbn><eisbn>9783981080148</eisbn><abstract>This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.</abstract><pub>IEEE</pub><doi>10.1109/DATE.2008.4484686</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1530-1591
ispartof 2008 Design, Automation and Test in Europe, 2008, p.200-205
issn 1530-1591
1558-1101
language eng
recordid cdi_ieee_primary_4484686
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Calculus
Delay
Digital video broadcasting
Heart
Network servers
Performance analysis
Power system interconnection
Telecommunication traffic
Traffic control
Upper bound
title Performance Analysis of SoC Architectures Based on Latency-Rate Servers
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T15%3A39%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Performance%20Analysis%20of%20SoC%20Architectures%20Based%20on%20Latency-Rate%20Servers&rft.btitle=2008%20Design,%20Automation%20and%20Test%20in%20Europe&rft.au=Vink,%20J.P.&rft.date=2008-03&rft.spage=200&rft.epage=205&rft.pages=200-205&rft.issn=1530-1591&rft.eissn=1558-1101&rft.isbn=3981080130&rft.isbn_list=9783981080131&rft_id=info:doi/10.1109/DATE.2008.4484686&rft_dat=%3Cieee_6IE%3E4484686%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=3981080149&rft.eisbn_list=9783981080148&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4484686&rfr_iscdi=true