Three-Dimensional Mold Flow in Stacked-Chip Scale Packages (S-CSP)

Stacked-chip scale package (S-CSP) technology enables the stacking of a wide range of different semiconductor devices. A fundamental goal of stacked-die packaging is to lower cost to the end user by it advantages of higher packaging density and better performance. In this paper, flow during encapsulation process in S-CSP is studied. A finite difference method based on Navier-Stokes equation adopted with Kawamura and Kuwahara technique is applied for the flow analysis in the chip cavity whereas a melt fronts are tracked directly by solving the volume of fluid (VOF) with pseudo-concentration method. The numerical model has been verified by comparing the prediction with experimental results. The simulation results show good agreement with experimental results.