Design Assists for Embedded Systems in the COINS Compiler Infrastructure
Program design of embedded systems requires special considerations such as compact code size, shorter addressing field, low cost parallelization, tuning to application field, and so on. COINS is a compiler infrastructure that makes compiler development easy by providing a code generator based on tar...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 69 |
---|---|
container_issue | |
container_start_page | 60 |
container_title | |
container_volume | |
creator | Watanabe, T. Fujise, T. Mori, K. Iwasawa, K. Nakata, I. |
description | Program design of embedded systems requires special considerations such as compact code size, shorter addressing field, low cost parallelization, tuning to application field, and so on. COINS is a compiler infrastructure that makes compiler development easy by providing a code generator based on target machine description for quick retargeting, and providing modularized analysis/optimization methods that can be called from user supplied compiler modules implementing new compiler features. Recently it has been extended to be able to select compact code size, to generate parallelized object code, to supply profiling information, etc. Such features to support embedded systems are discussed in this paper. |
doi_str_mv | 10.1109/IWIA.2007.13 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4450644</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4450644</ieee_id><sourcerecordid>4450644</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-1a0fd474a2205f3c1a17aa5b84073a077f173d736e60ed5d7361728dbfa6c7a93</originalsourceid><addsrcrecordid>eNotjs1OAjEURht_EhHZuXPTFxjs7W3nMksygkxCZIFGd6TQW61hgLTDgrcXo9_mnNXJJ8Q9qCGAqh6b92Y81ErREPBC9HRpdGEARpfiVlFZWVREH1eiBxapQK3xRgxy_lbnYWW1wZ6YPXGOnzs5zjnmLsuwT3LSrtl79nJ5yh23Wcad7L5Y1ovmZSnrfXuIW06y2YXkcpeOm-6Y-E5cB7fNPPhnX7xNJ6_1rJgvnpt6PC8ikO0KcCp4Q8ZprWzADTgg5-x6ZBShO_8NQOgJSy4Ve_trQHrk18GVG3IV9sXDXzcy8-qQYuvSaWWMVaUx-AMRg0xy</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Design Assists for Embedded Systems in the COINS Compiler Infrastructure</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Watanabe, T. ; Fujise, T. ; Mori, K. ; Iwasawa, K. ; Nakata, I.</creator><creatorcontrib>Watanabe, T. ; Fujise, T. ; Mori, K. ; Iwasawa, K. ; Nakata, I.</creatorcontrib><description>Program design of embedded systems requires special considerations such as compact code size, shorter addressing field, low cost parallelization, tuning to application field, and so on. COINS is a compiler infrastructure that makes compiler development easy by providing a code generator based on target machine description for quick retargeting, and providing modularized analysis/optimization methods that can be called from user supplied compiler modules implementing new compiler features. Recently it has been extended to be able to select compact code size, to generate parallelized object code, to supply profiling information, etc. Such features to support embedded systems are discussed in this paper.</description><identifier>ISSN: 1537-3223</identifier><identifier>ISBN: 076953077X</identifier><identifier>ISBN: 9780769530772</identifier><identifier>EISSN: 2642-4118</identifier><identifier>DOI: 10.1109/IWIA.2007.13</identifier><language>eng</language><publisher>IEEE</publisher><subject>Costs ; Embedded system ; Joining processes ; Large scale integration ; Operating systems ; Optimization methods ; Program processors ; Real time systems ; Runtime ; Size control</subject><ispartof>Innovative architecture for future generation high-performance processors and systems (iwia 2007), 2007, p.60-69</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4450644$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4450644$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Watanabe, T.</creatorcontrib><creatorcontrib>Fujise, T.</creatorcontrib><creatorcontrib>Mori, K.</creatorcontrib><creatorcontrib>Iwasawa, K.</creatorcontrib><creatorcontrib>Nakata, I.</creatorcontrib><title>Design Assists for Embedded Systems in the COINS Compiler Infrastructure</title><title>Innovative architecture for future generation high-performance processors and systems (iwia 2007)</title><addtitle>IWIA</addtitle><description>Program design of embedded systems requires special considerations such as compact code size, shorter addressing field, low cost parallelization, tuning to application field, and so on. COINS is a compiler infrastructure that makes compiler development easy by providing a code generator based on target machine description for quick retargeting, and providing modularized analysis/optimization methods that can be called from user supplied compiler modules implementing new compiler features. Recently it has been extended to be able to select compact code size, to generate parallelized object code, to supply profiling information, etc. Such features to support embedded systems are discussed in this paper.</description><subject>Costs</subject><subject>Embedded system</subject><subject>Joining processes</subject><subject>Large scale integration</subject><subject>Operating systems</subject><subject>Optimization methods</subject><subject>Program processors</subject><subject>Real time systems</subject><subject>Runtime</subject><subject>Size control</subject><issn>1537-3223</issn><issn>2642-4118</issn><isbn>076953077X</isbn><isbn>9780769530772</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjs1OAjEURht_EhHZuXPTFxjs7W3nMksygkxCZIFGd6TQW61hgLTDgrcXo9_mnNXJJ8Q9qCGAqh6b92Y81ErREPBC9HRpdGEARpfiVlFZWVREH1eiBxapQK3xRgxy_lbnYWW1wZ6YPXGOnzs5zjnmLsuwT3LSrtl79nJ5yh23Wcad7L5Y1ovmZSnrfXuIW06y2YXkcpeOm-6Y-E5cB7fNPPhnX7xNJ6_1rJgvnpt6PC8ikO0KcCp4Q8ZprWzADTgg5-x6ZBShO_8NQOgJSy4Ve_trQHrk18GVG3IV9sXDXzcy8-qQYuvSaWWMVaUx-AMRg0xy</recordid><startdate>200701</startdate><enddate>200701</enddate><creator>Watanabe, T.</creator><creator>Fujise, T.</creator><creator>Mori, K.</creator><creator>Iwasawa, K.</creator><creator>Nakata, I.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200701</creationdate><title>Design Assists for Embedded Systems in the COINS Compiler Infrastructure</title><author>Watanabe, T. ; Fujise, T. ; Mori, K. ; Iwasawa, K. ; Nakata, I.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-1a0fd474a2205f3c1a17aa5b84073a077f173d736e60ed5d7361728dbfa6c7a93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Costs</topic><topic>Embedded system</topic><topic>Joining processes</topic><topic>Large scale integration</topic><topic>Operating systems</topic><topic>Optimization methods</topic><topic>Program processors</topic><topic>Real time systems</topic><topic>Runtime</topic><topic>Size control</topic><toplevel>online_resources</toplevel><creatorcontrib>Watanabe, T.</creatorcontrib><creatorcontrib>Fujise, T.</creatorcontrib><creatorcontrib>Mori, K.</creatorcontrib><creatorcontrib>Iwasawa, K.</creatorcontrib><creatorcontrib>Nakata, I.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Watanabe, T.</au><au>Fujise, T.</au><au>Mori, K.</au><au>Iwasawa, K.</au><au>Nakata, I.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design Assists for Embedded Systems in the COINS Compiler Infrastructure</atitle><btitle>Innovative architecture for future generation high-performance processors and systems (iwia 2007)</btitle><stitle>IWIA</stitle><date>2007-01</date><risdate>2007</risdate><spage>60</spage><epage>69</epage><pages>60-69</pages><issn>1537-3223</issn><eissn>2642-4118</eissn><isbn>076953077X</isbn><isbn>9780769530772</isbn><abstract>Program design of embedded systems requires special considerations such as compact code size, shorter addressing field, low cost parallelization, tuning to application field, and so on. COINS is a compiler infrastructure that makes compiler development easy by providing a code generator based on target machine description for quick retargeting, and providing modularized analysis/optimization methods that can be called from user supplied compiler modules implementing new compiler features. Recently it has been extended to be able to select compact code size, to generate parallelized object code, to supply profiling information, etc. Such features to support embedded systems are discussed in this paper.</abstract><pub>IEEE</pub><doi>10.1109/IWIA.2007.13</doi><tpages>10</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1537-3223 |
ispartof | Innovative architecture for future generation high-performance processors and systems (iwia 2007), 2007, p.60-69 |
issn | 1537-3223 2642-4118 |
language | eng |
recordid | cdi_ieee_primary_4450644 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Costs Embedded system Joining processes Large scale integration Operating systems Optimization methods Program processors Real time systems Runtime Size control |
title | Design Assists for Embedded Systems in the COINS Compiler Infrastructure |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T19%3A12%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Design%20Assists%20for%20Embedded%20Systems%20in%20the%20COINS%20Compiler%20Infrastructure&rft.btitle=Innovative%20architecture%20for%20future%20generation%20high-performance%20processors%20and%20systems%20(iwia%202007)&rft.au=Watanabe,%20T.&rft.date=2007-01&rft.spage=60&rft.epage=69&rft.pages=60-69&rft.issn=1537-3223&rft.eissn=2642-4118&rft.isbn=076953077X&rft.isbn_list=9780769530772&rft_id=info:doi/10.1109/IWIA.2007.13&rft_dat=%3Cieee_6IE%3E4450644%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4450644&rfr_iscdi=true |