A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the wo...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 526 |
|---|---|
| container_issue | |
| container_start_page | 521 |
| container_title | |
| container_volume | |
| creator | Sambamurthy, S. Abraham, J.A. Tupuri, R.S. |
| description | We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error |
| doi_str_mv | 10.1109/VLSI.2008.56 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4450552</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4450552</ieee_id><sourcerecordid>4450552</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-12db8b23a0b8dce9c3e906b0665a433b42cdbb5f99e380b34ec430c35c7e79ba3</originalsourceid><addsrcrecordid>eNotj71OwzAURi1-JNrCxsbiF0i5iWMnHqu0QKUgUFtYK9u5KUZpXGKXkrcnEkzft5wjHUJuY5jGMcj793K9nCYA-ZSLMzJKWA6RkAk7J2PIhOQMcpZekFEMgkVSiOyKjL3_hIHgkI3Iz4yunD76QDfuEM3dqaXzvlV7a-irO2FHFz7YvQrWtfQZw4erXON2Pa1dR-fYqJ4WrvWhU7bFiq5wZ30YqE2nWl8Pp8RvbOgav47YBqsaWtjOHG3w1-SyVo3Hm_-dkLeHxaZ4isqXx2UxKyMbZzxEcVLpXCdMgc4rg9IwlCA0CMFVyphOE1NpzWspcUjXLEWTMjCMmwwzqRWbkLs_r0XE7aEbYrp-m6YcOE_YL4OiXvY</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Sambamurthy, S. ; Abraham, J.A. ; Tupuri, R.S.</creator><creatorcontrib>Sambamurthy, S. ; Abraham, J.A. ; Tupuri, R.S.</creatorcontrib><description>We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.</description><identifier>ISSN: 1063-9667</identifier><identifier>ISBN: 0769530834</identifier><identifier>ISBN: 9780769530833</identifier><identifier>EISSN: 2380-6923</identifier><identifier>DOI: 10.1109/VLSI.2008.56</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Circuit simulation ; Computer errors ; Delay estimation ; Energy consumption ; Frequency ; Libraries ; Registers ; Robustness ; Sequential circuits</subject><ispartof>21st International Conference on VLSI Design (VLSID 2008), 2008, p.521-526</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4450552$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4450552$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sambamurthy, S.</creatorcontrib><creatorcontrib>Abraham, J.A.</creatorcontrib><creatorcontrib>Tupuri, R.S.</creatorcontrib><title>A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits</title><title>21st International Conference on VLSI Design (VLSID 2008)</title><addtitle>VLSID</addtitle><description>We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.</description><subject>Capacitance</subject><subject>Circuit simulation</subject><subject>Computer errors</subject><subject>Delay estimation</subject><subject>Energy consumption</subject><subject>Frequency</subject><subject>Libraries</subject><subject>Registers</subject><subject>Robustness</subject><subject>Sequential circuits</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>0769530834</isbn><isbn>9780769530833</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj71OwzAURi1-JNrCxsbiF0i5iWMnHqu0QKUgUFtYK9u5KUZpXGKXkrcnEkzft5wjHUJuY5jGMcj793K9nCYA-ZSLMzJKWA6RkAk7J2PIhOQMcpZekFEMgkVSiOyKjL3_hIHgkI3Iz4yunD76QDfuEM3dqaXzvlV7a-irO2FHFz7YvQrWtfQZw4erXON2Pa1dR-fYqJ4WrvWhU7bFiq5wZ30YqE2nWl8Pp8RvbOgav47YBqsaWtjOHG3w1-SyVo3Hm_-dkLeHxaZ4isqXx2UxKyMbZzxEcVLpXCdMgc4rg9IwlCA0CMFVyphOE1NpzWspcUjXLEWTMjCMmwwzqRWbkLs_r0XE7aEbYrp-m6YcOE_YL4OiXvY</recordid><startdate>200801</startdate><enddate>200801</enddate><creator>Sambamurthy, S.</creator><creator>Abraham, J.A.</creator><creator>Tupuri, R.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200801</creationdate><title>A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits</title><author>Sambamurthy, S. ; Abraham, J.A. ; Tupuri, R.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-12db8b23a0b8dce9c3e906b0665a433b42cdbb5f99e380b34ec430c35c7e79ba3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Capacitance</topic><topic>Circuit simulation</topic><topic>Computer errors</topic><topic>Delay estimation</topic><topic>Energy consumption</topic><topic>Frequency</topic><topic>Libraries</topic><topic>Registers</topic><topic>Robustness</topic><topic>Sequential circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Sambamurthy, S.</creatorcontrib><creatorcontrib>Abraham, J.A.</creatorcontrib><creatorcontrib>Tupuri, R.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sambamurthy, S.</au><au>Abraham, J.A.</au><au>Tupuri, R.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits</atitle><btitle>21st International Conference on VLSI Design (VLSID 2008)</btitle><stitle>VLSID</stitle><date>2008-01</date><risdate>2008</risdate><spage>521</spage><epage>526</epage><pages>521-526</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>0769530834</isbn><isbn>9780769530833</isbn><abstract>We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.</abstract><pub>IEEE</pub><doi>10.1109/VLSI.2008.56</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1063-9667 |
| ispartof | 21st International Conference on VLSI Design (VLSID 2008), 2008, p.521-526 |
| issn | 1063-9667 2380-6923 |
| language | eng |
| recordid | cdi_ieee_primary_4450552 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance Circuit simulation Computer errors Delay estimation Energy consumption Frequency Libraries Registers Robustness Sequential circuits |
| title | A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T23%3A22%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Robust%20Top-Down%20Dynamic%20Power%20Estimation%20Methodology%20for%20Delay%20Constrained%20Register%20Transfer%20Level%20Sequential%20Circuits&rft.btitle=21st%20International%20Conference%20on%20VLSI%20Design%20(VLSID%202008)&rft.au=Sambamurthy,%20S.&rft.date=2008-01&rft.spage=521&rft.epage=526&rft.pages=521-526&rft.issn=1063-9667&rft.eissn=2380-6923&rft.isbn=0769530834&rft.isbn_list=9780769530833&rft_id=info:doi/10.1109/VLSI.2008.56&rft_dat=%3Cieee_6IE%3E4450552%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4450552&rfr_iscdi=true |