Compact Modeling of Suspended Gate FET

For the first time, a compact model for suspended gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical simulation approach combining ANSYS Multiphysi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chauhan, Y.S., Tsamados, D., Abele, N., Eggimann, C., Declercq, M., Ionescu, A.M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitance Circuit simulation Circuit testing Electrostatics FETs Hardware design languages Numerical simulation Switches Very large scale integration Voltage
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