$A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 \mu} CMOS Technology$

A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 \mu} CMOS Technology

In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing ma...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2008-02, Vol.43 (2), p.541-549
Hauptverfasser:	Kim, Byung-Guk, Kim, Lee-Sup, Byun, Sangjin, Yu, Hyun-Kyu
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth CMOS CMOS technology Coupling circuits Delay delay-locked loop (DLL) DEMUX Energy consumption Frequency conversion Inductors latch Latches Logic testing static frequency divider Timing
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