A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression
A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new archi...
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creator | Konda, M. Nakayama, T. Miyamoto, N. Ohmi, T. |
description | A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture. |
doi_str_mv | 10.1109/FPT.2007.4439277 |
format | Conference Proceeding |
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The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.</description><identifier>ISBN: 1424414717</identifier><identifier>ISBN: 9781424414710</identifier><identifier>EISBN: 9781424414727</identifier><identifier>EISBN: 1424414725</identifier><identifier>DOI: 10.1109/FPT.2007.4439277</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Degradation ; Field programmable gate arrays ; Hardware ; Image coding ; Layout ; Motion pictures ; Pipelines ; Transform coding ; Vector quantization</subject><ispartof>2007 International Conference on Field-Programmable Technology, 2007, p.325-328</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4439277$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4439277$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Konda, M.</creatorcontrib><creatorcontrib>Nakayama, T.</creatorcontrib><creatorcontrib>Miyamoto, N.</creatorcontrib><creatorcontrib>Ohmi, T.</creatorcontrib><title>A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression</title><title>2007 International Conference on Field-Programmable Technology</title><addtitle>FPT</addtitle><description>A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. 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The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.</abstract><pub>IEEE</pub><doi>10.1109/FPT.2007.4439277</doi><tpages>4</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Computer architecture Degradation Field programmable gate arrays Hardware Image coding Layout Motion pictures Pipelines Transform coding Vector quantization |
title | A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression |
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