A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression

A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new archi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Konda, M., Nakayama, T., Miyamoto, N., Ohmi, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 328
container_issue
container_start_page 325
container_title
container_volume
creator Konda, M.
Nakayama, T.
Miyamoto, N.
Ohmi, T.
description A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.
doi_str_mv 10.1109/FPT.2007.4439277
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4439277</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4439277</ieee_id><sourcerecordid>4439277</sourcerecordid><originalsourceid>FETCH-LOGICAL-i241t-1a55487c6f61d63d6bb6f3f66bc66ce529ed34d41e013359acfb8d6cf5c10a9c3</originalsourceid><addsrcrecordid>eNo1kF9LwzAURyMiqLPvgi_5Ap25TZq0j7NsU5g4R_V1pMmNRPpnpO2DfnoLnU-X3-FwHi4h98CWACx_3OzLZcKYWgrB80SpCxLlKgORCAFCJeqS3P4PUNck6vtvxhgoORFxQ_oVfdK1bg1a-olm6EL8Pup28L968F1L96Ez2PddoOvaN76daPtFD2jH1k4aLXRtxnp23WQdUNdx6Rukr90c8GYYA9Kia05hKk3sjlw5XfcYne-CfGzWZfEc7962L8VqF_tEwBCDTlORKSOdBCu5lVUlHXdSVkZKg2mSo-XCCkAGnKe5Nq7KrDQuNcB0bviCPMxdj4jHU_CNDj_H85_4HwIcXdE</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Konda, M. ; Nakayama, T. ; Miyamoto, N. ; Ohmi, T.</creator><creatorcontrib>Konda, M. ; Nakayama, T. ; Miyamoto, N. ; Ohmi, T.</creatorcontrib><description>A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.</description><identifier>ISBN: 1424414717</identifier><identifier>ISBN: 9781424414710</identifier><identifier>EISBN: 9781424414727</identifier><identifier>EISBN: 1424414725</identifier><identifier>DOI: 10.1109/FPT.2007.4439277</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Degradation ; Field programmable gate arrays ; Hardware ; Image coding ; Layout ; Motion pictures ; Pipelines ; Transform coding ; Vector quantization</subject><ispartof>2007 International Conference on Field-Programmable Technology, 2007, p.325-328</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4439277$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4439277$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Konda, M.</creatorcontrib><creatorcontrib>Nakayama, T.</creatorcontrib><creatorcontrib>Miyamoto, N.</creatorcontrib><creatorcontrib>Ohmi, T.</creatorcontrib><title>A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression</title><title>2007 International Conference on Field-Programmable Technology</title><addtitle>FPT</addtitle><description>A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.</description><subject>Computer architecture</subject><subject>Degradation</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Image coding</subject><subject>Layout</subject><subject>Motion pictures</subject><subject>Pipelines</subject><subject>Transform coding</subject><subject>Vector quantization</subject><isbn>1424414717</isbn><isbn>9781424414710</isbn><isbn>9781424414727</isbn><isbn>1424414725</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kF9LwzAURyMiqLPvgi_5Ap25TZq0j7NsU5g4R_V1pMmNRPpnpO2DfnoLnU-X3-FwHi4h98CWACx_3OzLZcKYWgrB80SpCxLlKgORCAFCJeqS3P4PUNck6vtvxhgoORFxQ_oVfdK1bg1a-olm6EL8Pup28L968F1L96Ez2PddoOvaN76daPtFD2jH1k4aLXRtxnp23WQdUNdx6Rukr90c8GYYA9Kia05hKk3sjlw5XfcYne-CfGzWZfEc7962L8VqF_tEwBCDTlORKSOdBCu5lVUlHXdSVkZKg2mSo-XCCkAGnKe5Nq7KrDQuNcB0bviCPMxdj4jHU_CNDj_H85_4HwIcXdE</recordid><startdate>200712</startdate><enddate>200712</enddate><creator>Konda, M.</creator><creator>Nakayama, T.</creator><creator>Miyamoto, N.</creator><creator>Ohmi, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200712</creationdate><title>A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression</title><author>Konda, M. ; Nakayama, T. ; Miyamoto, N. ; Ohmi, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-1a55487c6f61d63d6bb6f3f66bc66ce529ed34d41e013359acfb8d6cf5c10a9c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Computer architecture</topic><topic>Degradation</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Image coding</topic><topic>Layout</topic><topic>Motion pictures</topic><topic>Pipelines</topic><topic>Transform coding</topic><topic>Vector quantization</topic><toplevel>online_resources</toplevel><creatorcontrib>Konda, M.</creatorcontrib><creatorcontrib>Nakayama, T.</creatorcontrib><creatorcontrib>Miyamoto, N.</creatorcontrib><creatorcontrib>Ohmi, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Konda, M.</au><au>Nakayama, T.</au><au>Miyamoto, N.</au><au>Ohmi, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression</atitle><btitle>2007 International Conference on Field-Programmable Technology</btitle><stitle>FPT</stitle><date>2007-12</date><risdate>2007</risdate><spage>325</spage><epage>328</epage><pages>325-328</pages><isbn>1424414717</isbn><isbn>9781424414710</isbn><eisbn>9781424414727</eisbn><eisbn>1424414725</eisbn><abstract>A balanced vector-quantization (VQ) processor has been developed for real-time encoding of motion pictures (640times480 pixels) by using FPGA. The VQ processor employs a search algorithm for VQ encoding to reduce computational complexity and hardware volume. And this VQ processor employs a new architecture of distance calculation unit. By adopting the pipeline composition of each element, the number of distance calculation units could be reduced compared with fully parallel hardware architecture. Besides, in order to reduce memory size of codebook, 2048 template vectors consist of 512 basic template vectors, and the distance calculation units using pipeline composition are arranged in parallel for rotated template vectors. As a result, real-time VQ processor on FPGA is balanced architecture compared with the fully parallel architecture.</abstract><pub>IEEE</pub><doi>10.1109/FPT.2007.4439277</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1424414717
ispartof 2007 International Conference on Field-Programmable Technology, 2007, p.325-328
issn
language eng
recordid cdi_ieee_primary_4439277
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Computer architecture
Degradation
Field programmable gate arrays
Hardware
Image coding
Layout
Motion pictures
Pipelines
Transform coding
Vector quantization
title A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T18%3A14%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Balanced%20Vector-Quantization%20Processor%20Eliminating%20Redundant%20Calculation%20for%20Real-Time%20Motion%20Picture%20Compression&rft.btitle=2007%20International%20Conference%20on%20Field-Programmable%20Technology&rft.au=Konda,%20M.&rft.date=2007-12&rft.spage=325&rft.epage=328&rft.pages=325-328&rft.isbn=1424414717&rft.isbn_list=9781424414710&rft_id=info:doi/10.1109/FPT.2007.4439277&rft_dat=%3Cieee_6IE%3E4439277%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424414727&rft.eisbn_list=1424414725&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4439277&rfr_iscdi=true