High performance firmware architecture for FIR filtering in DSP processors

The paper presents a technique for implementing finite impulse response (FIR) filtering in last generation digital signal processors (DSP), which has been specifically designed and developed. Thanks to a fully assembler coded firmware that exploits at best the device resources, a maximum parallel da...

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Bibliographische Detailangaben

Hauptverfasser:	Scarpaci, S., Suardi, A., Geraci, A., Ripamonti, G.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Assembly Data processing Digital filters Digital signal processing Digital signal processors Filtering Finite impulse response filter Microprogramming Signal design Signal generators
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