Device Design and Optimization Considerations for Bulk FinFETs
Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI Fin...
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| Veröffentlicht in: | IEEE transactions on electron devices 2008-02, Vol.55 (2), p.609-615 |
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| container_title | IEEE transactions on electron devices |
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| creator | Manoj, C.R. Nagpal, M. Varghese, D. Rao, V.R. |
| description | Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs. |
| doi_str_mv | 10.1109/TED.2007.912996 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_4436001</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4436001</ieee_id><sourcerecordid>34413121</sourcerecordid><originalsourceid>FETCH-LOGICAL-c381t-835be8f4e7eb4865f8c342e86599befbbe3ca9f0c98565a7b91ee7f9c8f69e0c3</originalsourceid><addsrcrecordid>eNp9kT1PwzAQhi0EEqUwM7BESMCU1o4dx16QoB-AVKlLmS3HPSOXNCl2ggS_HrdFHRiY7uu50917CF0SPCAEy-FiMh5kGBcDSTIp-RHqkTwvUskZP0Y9jIlIJRX0FJ2FsIohZyzrofsxfDoDyRiCe6sTXS-T-aZ1a_etW9fUyaipg1uC30UhsY1PHrvqPZm6ejpZhHN0YnUV4OLX9tFrTI-e09n86WX0MEsNFaRNBc1LEJZBASUTPLfCUJZB9KQswZYlUKOlxUaKnOe6KCUBKKw0wnIJ2NA-utvP3fjmo4PQqrULBqpK19B0QUlMecYkE5G8_ZekjBFKMhLB6z_gqul8Ha9Qgmc5JUQWERruIeObEDxYtfFurf2XIlhtZVdRdrWVXe1ljx03v2N1MLqyXtfGhUNbRGmR7_a82nMOAA5lxiiPv6E_u26JmA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>862531197</pqid></control><display><type>article</type><title>Device Design and Optimization Considerations for Bulk FinFETs</title><source>IEEE Electronic Library (IEL)</source><creator>Manoj, C.R. ; Nagpal, M. ; Varghese, D. ; Rao, V.R.</creator><creatorcontrib>Manoj, C.R. ; Nagpal, M. ; Varghese, D. ; Rao, V.R.</creatorcontrib><description>Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2007.912996</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Bulk FinFET ; Design. Technologies. Operation analysis. Testing ; device parasitics ; Doping ; Doping profiles ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; FinFETs ; fringe capacitance ; Integrated circuits ; inverter delay ; Optimization ; Performance evaluation ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon on insulator technology ; SOI FinFET ; Solid modeling ; Transistors</subject><ispartof>IEEE transactions on electron devices, 2008-02, Vol.55 (2), p.609-615</ispartof><rights>2008 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c381t-835be8f4e7eb4865f8c342e86599befbbe3ca9f0c98565a7b91ee7f9c8f69e0c3</citedby><cites>FETCH-LOGICAL-c381t-835be8f4e7eb4865f8c342e86599befbbe3ca9f0c98565a7b91ee7f9c8f69e0c3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4436001$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4436001$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=20037548$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Manoj, C.R.</creatorcontrib><creatorcontrib>Nagpal, M.</creatorcontrib><creatorcontrib>Varghese, D.</creatorcontrib><creatorcontrib>Rao, V.R.</creatorcontrib><title>Device Design and Optimization Considerations for Bulk FinFETs</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.</description><subject>Applied sciences</subject><subject>Bulk FinFET</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>device parasitics</subject><subject>Doping</subject><subject>Doping profiles</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>FinFETs</subject><subject>fringe capacitance</subject><subject>Integrated circuits</subject><subject>inverter delay</subject><subject>Optimization</subject><subject>Performance evaluation</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon on insulator technology</subject><subject>SOI FinFET</subject><subject>Solid modeling</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kT1PwzAQhi0EEqUwM7BESMCU1o4dx16QoB-AVKlLmS3HPSOXNCl2ggS_HrdFHRiY7uu50917CF0SPCAEy-FiMh5kGBcDSTIp-RHqkTwvUskZP0Y9jIlIJRX0FJ2FsIohZyzrofsxfDoDyRiCe6sTXS-T-aZ1a_etW9fUyaipg1uC30UhsY1PHrvqPZm6ejpZhHN0YnUV4OLX9tFrTI-e09n86WX0MEsNFaRNBc1LEJZBASUTPLfCUJZB9KQswZYlUKOlxUaKnOe6KCUBKKw0wnIJ2NA-utvP3fjmo4PQqrULBqpK19B0QUlMecYkE5G8_ZekjBFKMhLB6z_gqul8Ha9Qgmc5JUQWERruIeObEDxYtfFurf2XIlhtZVdRdrWVXe1ljx03v2N1MLqyXtfGhUNbRGmR7_a82nMOAA5lxiiPv6E_u26JmA</recordid><startdate>20080201</startdate><enddate>20080201</enddate><creator>Manoj, C.R.</creator><creator>Nagpal, M.</creator><creator>Varghese, D.</creator><creator>Rao, V.R.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20080201</creationdate><title>Device Design and Optimization Considerations for Bulk FinFETs</title><author>Manoj, C.R. ; Nagpal, M. ; Varghese, D. ; Rao, V.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c381t-835be8f4e7eb4865f8c342e86599befbbe3ca9f0c98565a7b91ee7f9c8f69e0c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Applied sciences</topic><topic>Bulk FinFET</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>device parasitics</topic><topic>Doping</topic><topic>Doping profiles</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>FinFETs</topic><topic>fringe capacitance</topic><topic>Integrated circuits</topic><topic>inverter delay</topic><topic>Optimization</topic><topic>Performance evaluation</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon on insulator technology</topic><topic>SOI FinFET</topic><topic>Solid modeling</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Manoj, C.R.</creatorcontrib><creatorcontrib>Nagpal, M.</creatorcontrib><creatorcontrib>Varghese, D.</creatorcontrib><creatorcontrib>Rao, V.R.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Manoj, C.R.</au><au>Nagpal, M.</au><au>Varghese, D.</au><au>Rao, V.R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Device Design and Optimization Considerations for Bulk FinFETs</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2008-02-01</date><risdate>2008</risdate><volume>55</volume><issue>2</issue><spage>609</spage><epage>615</epage><pages>609-615</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2007.912996</doi><tpages>7</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Bulk FinFET Design. Technologies. Operation analysis. Testing device parasitics Doping Doping profiles Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology FinFETs fringe capacitance Integrated circuits inverter delay Optimization Performance evaluation Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon on insulator technology SOI FinFET Solid modeling Transistors |
| title | Device Design and Optimization Considerations for Bulk FinFETs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T18%3A32%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Device%20Design%20and%20Optimization%20Considerations%20for%20Bulk%20FinFETs&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Manoj,%20C.R.&rft.date=2008-02-01&rft.volume=55&rft.issue=2&rft.spage=609&rft.epage=615&rft.pages=609-615&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2007.912996&rft_dat=%3Cproquest_RIE%3E34413121%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=862531197&rft_id=info:pmid/&rft_ieee_id=4436001&rfr_iscdi=true |