Molded underfill technology for low-k flip chip packages
Low-k dielectrics materials in the active layers on the chip surface has become a hot topic as most 90 nm devices and all 65 nm devices utilize low-k dielectrics materials. Low-k dielectrics materials provide a significant increase in performance of the devices but low-k materials have very low mech...
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creator | Wen-Tsung Tseng Ho-Yi Tsai Chiu, S. Hsiao, C.S. |
description | Low-k dielectrics materials in the active layers on the chip surface has become a hot topic as most 90 nm devices and all 65 nm devices utilize low-k dielectrics materials. Low-k dielectrics materials provide a significant increase in performance of the devices but low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in low strength and poor adhesion qualities of the low-k dielectric materials. These lead to a unique set of mechanical issues when low-k die are packaged, the reliability of low-k flip chip packaging has become a critical issue. The coefficient of thermal expansion (CTE) mismatch between the silicon die and the substrate produces a bending or curvature of the assembly upon changes of temperature. This type of thermal/mechanical stress can lead to solder bump fatigue, delamination of the low-k dielectrics materials and the failure of the electronic package. Due to the mechanical sensitivity of the low-k material, stresses induced by the package has been demonstrated to exasperate the problem. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. Thence, there is a need to use better technology to improve these problems, new molding underfill flip chip ball grid arrays (terminator FCBGA ) structure is developed. It uses hydrodynamic pressure of a mold press to transfer molten molding underfill material into the flip chip undergap, Therefore it does not have the same limitation as the conventional liquid capillary underfill (CUF) and the biggest advantage is its better coplanarity, high throughput , low stress , stronger bump protection, better solder joint capability and same thermal performance, especially for large package size and large die size. New molding underfill structure terminator FCBGA can provide strong bump protection and reach high reliability performance due to epoxy molding compound (EMC) low coefficient of thermal expansion (CTE) and high modulus. This kind of structure can also be applied all kind of bump composition such as tin-lead, high lead, and lead free. Furthermore, this paper also describes the process and reliability validation result. |
doi_str_mv | 10.1109/IMPACT.2007.4433630 |
format | Conference Proceeding |
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Low-k dielectrics materials provide a significant increase in performance of the devices but low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in low strength and poor adhesion qualities of the low-k dielectric materials. These lead to a unique set of mechanical issues when low-k die are packaged, the reliability of low-k flip chip packaging has become a critical issue. The coefficient of thermal expansion (CTE) mismatch between the silicon die and the substrate produces a bending or curvature of the assembly upon changes of temperature. This type of thermal/mechanical stress can lead to solder bump fatigue, delamination of the low-k dielectrics materials and the failure of the electronic package. Due to the mechanical sensitivity of the low-k material, stresses induced by the package has been demonstrated to exasperate the problem. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. Thence, there is a need to use better technology to improve these problems, new molding underfill flip chip ball grid arrays (terminator FCBGA ) structure is developed. It uses hydrodynamic pressure of a mold press to transfer molten molding underfill material into the flip chip undergap, Therefore it does not have the same limitation as the conventional liquid capillary underfill (CUF) and the biggest advantage is its better coplanarity, high throughput , low stress , stronger bump protection, better solder joint capability and same thermal performance, especially for large package size and large die size. New molding underfill structure terminator FCBGA can provide strong bump protection and reach high reliability performance due to epoxy molding compound (EMC) low coefficient of thermal expansion (CTE) and high modulus. This kind of structure can also be applied all kind of bump composition such as tin-lead, high lead, and lead free. Furthermore, this paper also describes the process and reliability validation result.</description><identifier>ISSN: 2150-5934</identifier><identifier>ISBN: 1424416361</identifier><identifier>ISBN: 9781424416363</identifier><identifier>EISSN: 2150-5942</identifier><identifier>EISBN: 9781424416370</identifier><identifier>EISBN: 142441637X</identifier><identifier>DOI: 10.1109/IMPACT.2007.4433630</identifier><language>eng</language><publisher>IEEE</publisher><subject>coplanarity ; Dielectric materials ; Electronic packaging thermal management ; Electronics packaging ; Environmentally friendly manufacturing techniques ; Flip chip ; Lead ; Low-k ; molding underfill ; Protection ; Thermal expansion ; Thermal stresses ; Throughput</subject><ispartof>2007 International Microsystems, Packaging, Assembly and Circuits Technology, 2007, p.335-337</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4433630$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4433630$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wen-Tsung Tseng</creatorcontrib><creatorcontrib>Ho-Yi Tsai</creatorcontrib><creatorcontrib>Chiu, S.</creatorcontrib><creatorcontrib>Hsiao, C.S.</creatorcontrib><title>Molded underfill technology for low-k flip chip packages</title><title>2007 International Microsystems, Packaging, Assembly and Circuits Technology</title><addtitle>IMPACT</addtitle><description>Low-k dielectrics materials in the active layers on the chip surface has become a hot topic as most 90 nm devices and all 65 nm devices utilize low-k dielectrics materials. Low-k dielectrics materials provide a significant increase in performance of the devices but low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in low strength and poor adhesion qualities of the low-k dielectric materials. These lead to a unique set of mechanical issues when low-k die are packaged, the reliability of low-k flip chip packaging has become a critical issue. The coefficient of thermal expansion (CTE) mismatch between the silicon die and the substrate produces a bending or curvature of the assembly upon changes of temperature. This type of thermal/mechanical stress can lead to solder bump fatigue, delamination of the low-k dielectrics materials and the failure of the electronic package. Due to the mechanical sensitivity of the low-k material, stresses induced by the package has been demonstrated to exasperate the problem. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. Thence, there is a need to use better technology to improve these problems, new molding underfill flip chip ball grid arrays (terminator FCBGA ) structure is developed. It uses hydrodynamic pressure of a mold press to transfer molten molding underfill material into the flip chip undergap, Therefore it does not have the same limitation as the conventional liquid capillary underfill (CUF) and the biggest advantage is its better coplanarity, high throughput , low stress , stronger bump protection, better solder joint capability and same thermal performance, especially for large package size and large die size. New molding underfill structure terminator FCBGA can provide strong bump protection and reach high reliability performance due to epoxy molding compound (EMC) low coefficient of thermal expansion (CTE) and high modulus. This kind of structure can also be applied all kind of bump composition such as tin-lead, high lead, and lead free. Furthermore, this paper also describes the process and reliability validation result.</description><subject>coplanarity</subject><subject>Dielectric materials</subject><subject>Electronic packaging thermal management</subject><subject>Electronics packaging</subject><subject>Environmentally friendly manufacturing techniques</subject><subject>Flip chip</subject><subject>Lead</subject><subject>Low-k</subject><subject>molding underfill</subject><subject>Protection</subject><subject>Thermal expansion</subject><subject>Thermal stresses</subject><subject>Throughput</subject><issn>2150-5934</issn><issn>2150-5942</issn><isbn>1424416361</isbn><isbn>9781424416363</isbn><isbn>9781424416370</isbn><isbn>142441637X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kEtrwkAUhacvqLX5BW7yB5LemXvntRTpQ1DahV3LmLnR1KmRxFL89xVquzln8cEH5wgxklBKCf5hOn8bTxalArAlEaJBuBCZt06SIpIGLVyKgZIaCu1JXYm7P2Dk9T9AuhVZ338AAIIEQhoIN29T5Jh_7SJ3dZNSfuBqs2tTuz7mddvlqf0utnmdmn1ebU6xD9U2rLm_Fzd1SD1n5x6K96fHxeSlmL0-TyfjWdFIqw-FsaRRelRs2JG0nj3Wjr0lhUaBr0KQPurqNM3FVWVr7YMmE9GtLLuocShGv96GmZf7rvkM3XF5PgF_AFZqSoQ</recordid><startdate>200710</startdate><enddate>200710</enddate><creator>Wen-Tsung Tseng</creator><creator>Ho-Yi Tsai</creator><creator>Chiu, S.</creator><creator>Hsiao, C.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200710</creationdate><title>Molded underfill technology for low-k flip chip packages</title><author>Wen-Tsung Tseng ; Ho-Yi Tsai ; Chiu, S. ; Hsiao, C.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-674531932e6e84179e93f8e974236209caa19d5c2008dbc7f59a546d38b7e8d53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>coplanarity</topic><topic>Dielectric materials</topic><topic>Electronic packaging thermal management</topic><topic>Electronics packaging</topic><topic>Environmentally friendly manufacturing techniques</topic><topic>Flip chip</topic><topic>Lead</topic><topic>Low-k</topic><topic>molding underfill</topic><topic>Protection</topic><topic>Thermal expansion</topic><topic>Thermal stresses</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Wen-Tsung Tseng</creatorcontrib><creatorcontrib>Ho-Yi Tsai</creatorcontrib><creatorcontrib>Chiu, S.</creatorcontrib><creatorcontrib>Hsiao, C.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wen-Tsung Tseng</au><au>Ho-Yi Tsai</au><au>Chiu, S.</au><au>Hsiao, C.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Molded underfill technology for low-k flip chip packages</atitle><btitle>2007 International Microsystems, Packaging, Assembly and Circuits Technology</btitle><stitle>IMPACT</stitle><date>2007-10</date><risdate>2007</risdate><spage>335</spage><epage>337</epage><pages>335-337</pages><issn>2150-5934</issn><eissn>2150-5942</eissn><isbn>1424416361</isbn><isbn>9781424416363</isbn><eisbn>9781424416370</eisbn><eisbn>142441637X</eisbn><abstract>Low-k dielectrics materials in the active layers on the chip surface has become a hot topic as most 90 nm devices and all 65 nm devices utilize low-k dielectrics materials. Low-k dielectrics materials provide a significant increase in performance of the devices but low-k materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in low strength and poor adhesion qualities of the low-k dielectric materials. These lead to a unique set of mechanical issues when low-k die are packaged, the reliability of low-k flip chip packaging has become a critical issue. The coefficient of thermal expansion (CTE) mismatch between the silicon die and the substrate produces a bending or curvature of the assembly upon changes of temperature. This type of thermal/mechanical stress can lead to solder bump fatigue, delamination of the low-k dielectrics materials and the failure of the electronic package. Due to the mechanical sensitivity of the low-k material, stresses induced by the package has been demonstrated to exasperate the problem. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. Thence, there is a need to use better technology to improve these problems, new molding underfill flip chip ball grid arrays (terminator FCBGA ) structure is developed. It uses hydrodynamic pressure of a mold press to transfer molten molding underfill material into the flip chip undergap, Therefore it does not have the same limitation as the conventional liquid capillary underfill (CUF) and the biggest advantage is its better coplanarity, high throughput , low stress , stronger bump protection, better solder joint capability and same thermal performance, especially for large package size and large die size. New molding underfill structure terminator FCBGA can provide strong bump protection and reach high reliability performance due to epoxy molding compound (EMC) low coefficient of thermal expansion (CTE) and high modulus. This kind of structure can also be applied all kind of bump composition such as tin-lead, high lead, and lead free. Furthermore, this paper also describes the process and reliability validation result.</abstract><pub>IEEE</pub><doi>10.1109/IMPACT.2007.4433630</doi><tpages>3</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | coplanarity Dielectric materials Electronic packaging thermal management Electronics packaging Environmentally friendly manufacturing techniques Flip chip Lead Low-k molding underfill Protection Thermal expansion Thermal stresses Throughput |
title | Molded underfill technology for low-k flip chip packages |
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