A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers
This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers wit...
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| creator | Maebashi, T. Nakamura, N. Nakayama, S. Miyakawa, N. |
| description | This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent. |
| doi_str_mv | 10.1109/ESSDERC.2007.4430925 |
| format | Conference Proceeding |
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Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. 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The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent.</description><subject>Bismuth</subject><subject>CMOS technology</subject><subject>Conductivity</subject><subject>Electric resistance</subject><subject>Electrodes</subject><subject>Fabrication</subject><subject>Isolation technology</subject><subject>Substrates</subject><subject>Wafer bonding</subject><subject>Wet etching</subject><issn>1930-8876</issn><isbn>1424411238</isbn><isbn>9781424411238</isbn><isbn>1424411246</isbn><isbn>9781424411245</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUNtOAjEUrFETAf0CfegPFNttu20fCeIlITERfSa9nEJ12TXbKuHvJUL0aeZMZiY5g9ANo2PGqLmdLRZ3s5fpuKJUjYXg1FTyBA2ZqIRgrBL16f_B9RkaMMMp0VrVF2iY8zulknOhB2g7wS1scbSuT96W1LV4A2XdBRy7Hm--mpJIY3fQ41ys_4CAA3wnDxl_5dSu8NZG6EnpyC_5MxXw67ZrutUOO5v3wr5Xk9T69SGRL9F5tE2GqyOO0Nv97HX6SObPD0_TyZwkpmQhKkQnTYzOe1aZIF0UtaAiKA3SS2mo90EYb5lRSkoPRjnv9o_xymkjasdH6PrQmwBg-dmnje13y-Ni_AfOyGBr</recordid><startdate>200709</startdate><enddate>200709</enddate><creator>Maebashi, T.</creator><creator>Nakamura, N.</creator><creator>Nakayama, S.</creator><creator>Miyakawa, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200709</creationdate><title>A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers</title><author>Maebashi, T. ; Nakamura, N. ; Nakayama, S. ; Miyakawa, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-7dfb59ffbcc129d5bf46404d78e5c5590ccd49ca197755ce97bcb34832b8946b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Bismuth</topic><topic>CMOS technology</topic><topic>Conductivity</topic><topic>Electric resistance</topic><topic>Electrodes</topic><topic>Fabrication</topic><topic>Isolation technology</topic><topic>Substrates</topic><topic>Wafer bonding</topic><topic>Wet etching</topic><toplevel>online_resources</toplevel><creatorcontrib>Maebashi, T.</creatorcontrib><creatorcontrib>Nakamura, N.</creatorcontrib><creatorcontrib>Nakayama, S.</creatorcontrib><creatorcontrib>Miyakawa, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maebashi, T.</au><au>Nakamura, N.</au><au>Nakayama, S.</au><au>Miyakawa, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers</atitle><btitle>ESSDERC 2007 - 37th European Solid State Device Research Conference</btitle><stitle>ESSDERC</stitle><date>2007-09</date><risdate>2007</risdate><spage>251</spage><epage>254</epage><pages>251-254</pages><issn>1930-8876</issn><isbn>1424411238</isbn><isbn>9781424411238</isbn><eisbn>1424411246</eisbn><eisbn>9781424411245</eisbn><abstract>This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent.</abstract><pub>IEEE</pub><doi>10.1109/ESSDERC.2007.4430925</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1930-8876 |
| ispartof | ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007, p.251-254 |
| issn | 1930-8876 |
| language | eng |
| recordid | cdi_ieee_primary_4430925 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bismuth CMOS technology Conductivity Electric resistance Electrodes Fabrication Isolation technology Substrates Wafer bonding Wet etching |
| title | A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers |
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