A 512 mb 2-channel mobile DRAM (oneDRAM™) with shared memory array

A 1.8 V, 512 Mb two-channel synchronous mobile DDR SDRAM (OneDRAMtrade) with 333 Mbps/pin was designed, with 90 nm technology. The device can operate as 2 separate mobile DDR SDRAMs through each channel because of its exclusive accessibility from each channel to dedicated memory arrays. A new contro...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kyungwoo Nam, Jung-Sik Kim, Chi Sung Oh, Hangu Sohn, Dong Hyuk Lee, Changho Lee, Sooyoung Kim, Jong-Wook Park, Yongjun Kim, Mijo Kim, Jinkuk Kim, Hocheol Lee, Jinhyoung Kwon, Dong Il Seo, Young-Hyun Jun, Kinam Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 207
container_issue
container_start_page 204
container_title
container_volume
creator Kyungwoo Nam
Jung-Sik Kim
Chi Sung Oh
Hangu Sohn
Dong Hyuk Lee
Changho Lee
Sooyoung Kim
Jong-Wook Park
Yongjun Kim
Mijo Kim
Jinkuk Kim
Hocheol Lee
Jinhyoung Kwon
Dong Il Seo
Young-Hyun Jun
Kinam Kim
description A 1.8 V, 512 Mb two-channel synchronous mobile DDR SDRAM (OneDRAMtrade) with 333 Mbps/pin was designed, with 90 nm technology. The device can operate as 2 separate mobile DDR SDRAMs through each channel because of its exclusive accessibility from each channel to dedicated memory arrays. A new control scheme is proposed to exchange data between two channels by sharing one common memory array. The shared memory array control scheme is based on direct addressing mode to achieve compatibility with normal SDRAM interface together with fast data transfer speed between two channels.
doi_str_mv 10.1109/ASSCC.2007.4425766
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4425766</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4425766</ieee_id><sourcerecordid>4425766</sourcerecordid><originalsourceid>FETCH-ieee_primary_44257663</originalsourceid><addsrcrecordid>eNpjYJAyNNAzNDSw1HcMDnZ21jMyMDDXMzExMjU3M2Nk4DI0MTIxMTQ2MzBlhnNMLQ05GHiLi7MMDAwMzc2AIkacDC6OCqaGRgq5SQpGuskZiXl5qTkKuflJmTmpCi5Bjr4KGvl5qSDGo5ZFmgrlmSUZCsUZiUWpKQq5qbn5RZUKiUVFiZU8DKxpiTnFqbxQmptB2s01xNlDNzM1NTW-oCgzN7GoMh7qOmP8sgCDmzqB</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 512 mb 2-channel mobile DRAM (oneDRAM™) with shared memory array</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kyungwoo Nam ; Jung-Sik Kim ; Chi Sung Oh ; Hangu Sohn ; Dong Hyuk Lee ; Changho Lee ; Sooyoung Kim ; Jong-Wook Park ; Yongjun Kim ; Mijo Kim ; Jinkuk Kim ; Hocheol Lee ; Jinhyoung Kwon ; Dong Il Seo ; Young-Hyun Jun ; Kinam Kim</creator><creatorcontrib>Kyungwoo Nam ; Jung-Sik Kim ; Chi Sung Oh ; Hangu Sohn ; Dong Hyuk Lee ; Changho Lee ; Sooyoung Kim ; Jong-Wook Park ; Yongjun Kim ; Mijo Kim ; Jinkuk Kim ; Hocheol Lee ; Jinhyoung Kwon ; Dong Il Seo ; Young-Hyun Jun ; Kinam Kim</creatorcontrib><description>A 1.8 V, 512 Mb two-channel synchronous mobile DDR SDRAM (OneDRAMtrade) with 333 Mbps/pin was designed, with 90 nm technology. The device can operate as 2 separate mobile DDR SDRAMs through each channel because of its exclusive accessibility from each channel to dedicated memory arrays. A new control scheme is proposed to exchange data between two channels by sharing one common memory array. The shared memory array control scheme is based on direct addressing mode to achieve compatibility with normal SDRAM interface together with fast data transfer speed between two channels.</description><identifier>ISBN: 1424413591</identifier><identifier>ISBN: 9781424413591</identifier><identifier>EISBN: 1424413605</identifier><identifier>EISBN: 9781424413607</identifier><identifier>DOI: 10.1109/ASSCC.2007.4425766</identifier><language>eng</language><publisher>IEEE</publisher><subject>Control systems ; DRAM chips ; Modems ; Multimedia systems ; Pins ; Process control ; Random access memory ; SDRAM ; Solid state circuit design ; Solid state circuits</subject><ispartof>2007 IEEE Asian Solid-State Circuits Conference, 2007, p.204-207</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4425766$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27908,54903</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4425766$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kyungwoo Nam</creatorcontrib><creatorcontrib>Jung-Sik Kim</creatorcontrib><creatorcontrib>Chi Sung Oh</creatorcontrib><creatorcontrib>Hangu Sohn</creatorcontrib><creatorcontrib>Dong Hyuk Lee</creatorcontrib><creatorcontrib>Changho Lee</creatorcontrib><creatorcontrib>Sooyoung Kim</creatorcontrib><creatorcontrib>Jong-Wook Park</creatorcontrib><creatorcontrib>Yongjun Kim</creatorcontrib><creatorcontrib>Mijo Kim</creatorcontrib><creatorcontrib>Jinkuk Kim</creatorcontrib><creatorcontrib>Hocheol Lee</creatorcontrib><creatorcontrib>Jinhyoung Kwon</creatorcontrib><creatorcontrib>Dong Il Seo</creatorcontrib><creatorcontrib>Young-Hyun Jun</creatorcontrib><creatorcontrib>Kinam Kim</creatorcontrib><title>A 512 mb 2-channel mobile DRAM (oneDRAM™) with shared memory array</title><title>2007 IEEE Asian Solid-State Circuits Conference</title><addtitle>ASSCC</addtitle><description>A 1.8 V, 512 Mb two-channel synchronous mobile DDR SDRAM (OneDRAMtrade) with 333 Mbps/pin was designed, with 90 nm technology. The device can operate as 2 separate mobile DDR SDRAMs through each channel because of its exclusive accessibility from each channel to dedicated memory arrays. A new control scheme is proposed to exchange data between two channels by sharing one common memory array. The shared memory array control scheme is based on direct addressing mode to achieve compatibility with normal SDRAM interface together with fast data transfer speed between two channels.</description><subject>Control systems</subject><subject>DRAM chips</subject><subject>Modems</subject><subject>Multimedia systems</subject><subject>Pins</subject><subject>Process control</subject><subject>Random access memory</subject><subject>SDRAM</subject><subject>Solid state circuit design</subject><subject>Solid state circuits</subject><isbn>1424413591</isbn><isbn>9781424413591</isbn><isbn>1424413605</isbn><isbn>9781424413607</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYJAyNNAzNDSw1HcMDnZ21jMyMDDXMzExMjU3M2Nk4DI0MTIxMTQ2MzBlhnNMLQ05GHiLi7MMDAwMzc2AIkacDC6OCqaGRgq5SQpGuskZiXl5qTkKuflJmTmpCi5Bjr4KGvl5qSDGo5ZFmgrlmSUZCsUZiUWpKQq5qbn5RZUKiUVFiZU8DKxpiTnFqbxQmptB2s01xNlDNzM1NTW-oCgzN7GoMh7qOmP8sgCDmzqB</recordid><startdate>200711</startdate><enddate>200711</enddate><creator>Kyungwoo Nam</creator><creator>Jung-Sik Kim</creator><creator>Chi Sung Oh</creator><creator>Hangu Sohn</creator><creator>Dong Hyuk Lee</creator><creator>Changho Lee</creator><creator>Sooyoung Kim</creator><creator>Jong-Wook Park</creator><creator>Yongjun Kim</creator><creator>Mijo Kim</creator><creator>Jinkuk Kim</creator><creator>Hocheol Lee</creator><creator>Jinhyoung Kwon</creator><creator>Dong Il Seo</creator><creator>Young-Hyun Jun</creator><creator>Kinam Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200711</creationdate><title>A 512 mb 2-channel mobile DRAM (oneDRAM™) with shared memory array</title><author>Kyungwoo Nam ; Jung-Sik Kim ; Chi Sung Oh ; Hangu Sohn ; Dong Hyuk Lee ; Changho Lee ; Sooyoung Kim ; Jong-Wook Park ; Yongjun Kim ; Mijo Kim ; Jinkuk Kim ; Hocheol Lee ; Jinhyoung Kwon ; Dong Il Seo ; Young-Hyun Jun ; Kinam Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_44257663</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Control systems</topic><topic>DRAM chips</topic><topic>Modems</topic><topic>Multimedia systems</topic><topic>Pins</topic><topic>Process control</topic><topic>Random access memory</topic><topic>SDRAM</topic><topic>Solid state circuit design</topic><topic>Solid state circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Kyungwoo Nam</creatorcontrib><creatorcontrib>Jung-Sik Kim</creatorcontrib><creatorcontrib>Chi Sung Oh</creatorcontrib><creatorcontrib>Hangu Sohn</creatorcontrib><creatorcontrib>Dong Hyuk Lee</creatorcontrib><creatorcontrib>Changho Lee</creatorcontrib><creatorcontrib>Sooyoung Kim</creatorcontrib><creatorcontrib>Jong-Wook Park</creatorcontrib><creatorcontrib>Yongjun Kim</creatorcontrib><creatorcontrib>Mijo Kim</creatorcontrib><creatorcontrib>Jinkuk Kim</creatorcontrib><creatorcontrib>Hocheol Lee</creatorcontrib><creatorcontrib>Jinhyoung Kwon</creatorcontrib><creatorcontrib>Dong Il Seo</creatorcontrib><creatorcontrib>Young-Hyun Jun</creatorcontrib><creatorcontrib>Kinam Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kyungwoo Nam</au><au>Jung-Sik Kim</au><au>Chi Sung Oh</au><au>Hangu Sohn</au><au>Dong Hyuk Lee</au><au>Changho Lee</au><au>Sooyoung Kim</au><au>Jong-Wook Park</au><au>Yongjun Kim</au><au>Mijo Kim</au><au>Jinkuk Kim</au><au>Hocheol Lee</au><au>Jinhyoung Kwon</au><au>Dong Il Seo</au><au>Young-Hyun Jun</au><au>Kinam Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 512 mb 2-channel mobile DRAM (oneDRAM™) with shared memory array</atitle><btitle>2007 IEEE Asian Solid-State Circuits Conference</btitle><stitle>ASSCC</stitle><date>2007-11</date><risdate>2007</risdate><spage>204</spage><epage>207</epage><pages>204-207</pages><isbn>1424413591</isbn><isbn>9781424413591</isbn><eisbn>1424413605</eisbn><eisbn>9781424413607</eisbn><abstract>A 1.8 V, 512 Mb two-channel synchronous mobile DDR SDRAM (OneDRAMtrade) with 333 Mbps/pin was designed, with 90 nm technology. The device can operate as 2 separate mobile DDR SDRAMs through each channel because of its exclusive accessibility from each channel to dedicated memory arrays. A new control scheme is proposed to exchange data between two channels by sharing one common memory array. The shared memory array control scheme is based on direct addressing mode to achieve compatibility with normal SDRAM interface together with fast data transfer speed between two channels.</abstract><pub>IEEE</pub><doi>10.1109/ASSCC.2007.4425766</doi></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1424413591
ispartof 2007 IEEE Asian Solid-State Circuits Conference, 2007, p.204-207
issn
language eng
recordid cdi_ieee_primary_4425766
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Control systems
DRAM chips
Modems
Multimedia systems
Pins
Process control
Random access memory
SDRAM
Solid state circuit design
Solid state circuits
title A 512 mb 2-channel mobile DRAM (oneDRAM™) with shared memory array
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T06%3A51%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20512%20mb%202-channel%20mobile%20DRAM%20(oneDRAM%E2%84%A2)%20with%20shared%20memory%20array&rft.btitle=2007%20IEEE%20Asian%20Solid-State%20Circuits%20Conference&rft.au=Kyungwoo%20Nam&rft.date=2007-11&rft.spage=204&rft.epage=207&rft.pages=204-207&rft.isbn=1424413591&rft.isbn_list=9781424413591&rft_id=info:doi/10.1109/ASSCC.2007.4425766&rft_dat=%3Cieee_6IE%3E4425766%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424413605&rft.eisbn_list=9781424413607&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4425766&rfr_iscdi=true