Record RF performance of 45-nm SOI CMOS Technology
We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak f T 's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to...
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| creator | Sungjae Lee Jagannathan, B. Narasimha, S. Chou, A. Zamdmer, N. Johnson, J. Williams, R. Wagner, L. Jonghae Kim Plouchart, J.-O. Pekarik, J. Springer, S. Freeman, G. |
| description | We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak f T 's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured f T 's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak f T of 245 GHz with no degradation in critical analog figures of merit, such as self-gain. |
| doi_str_mv | 10.1109/IEDM.2007.4418916 |
| format | Conference Proceeding |
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RF performance scaling with channel length and layout optimization is demonstrated. Peak f T 's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured f T 's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak f T of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.</description><subject>Capacitance measurement</subject><subject>CMOS technology</subject><subject>FETs</subject><subject>Insulation</subject><subject>Leakage current</subject><subject>Length measurement</subject><subject>Parasitic capacitance</subject><subject>Radio frequency</subject><subject>Silicon on insulator technology</subject><subject>Wiring</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>1424415071</isbn><isbn>9781424415076</isbn><isbn>142441508X</isbn><isbn>9781424415083</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFj8tqwkAYhac3aGp9gNLNvMCk_z_3WZZU24ASUAvuZDKZaS0mkdiNb69QoavD4Tt8cAh5QsgRwb2Uk7d5zgFMLiVah_qKPKDk56LArq9JxlFpBmjWN__A4C3JALVg6NDek_Hh8ANwHmmJ0mSEL2Loh4YupnQfh9QPre9CpH2iUrGupcuqpMW8WtJVDN9dv-u_jo_kLvndIY4vOSKf08mq-GCz6r0sXmcscJC_LBrkOnmXbC248MYpGVSyRgvHDTbSJRXAgWyCMrUVtUETfXIOdG0tBC9G5PnPu40xbvbDtvXDcXP5Lk4srkXc</recordid><startdate>200712</startdate><enddate>200712</enddate><creator>Sungjae Lee</creator><creator>Jagannathan, B.</creator><creator>Narasimha, S.</creator><creator>Chou, A.</creator><creator>Zamdmer, N.</creator><creator>Johnson, J.</creator><creator>Williams, R.</creator><creator>Wagner, L.</creator><creator>Jonghae Kim</creator><creator>Plouchart, J.-O.</creator><creator>Pekarik, J.</creator><creator>Springer, S.</creator><creator>Freeman, G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200712</creationdate><title>Record RF performance of 45-nm SOI CMOS Technology</title><author>Sungjae Lee ; Jagannathan, B. ; Narasimha, S. ; Chou, A. ; Zamdmer, N. ; Johnson, J. ; Williams, R. ; Wagner, L. ; Jonghae Kim ; Plouchart, J.-O. ; Pekarik, J. ; Springer, S. ; Freeman, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c204t-e7126fa9f8b323a7954c5f87639271d49f5c0904dc57b83b717eaf9906b880ca3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Capacitance measurement</topic><topic>CMOS technology</topic><topic>FETs</topic><topic>Insulation</topic><topic>Leakage current</topic><topic>Length measurement</topic><topic>Parasitic capacitance</topic><topic>Radio frequency</topic><topic>Silicon on insulator technology</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Sungjae Lee</creatorcontrib><creatorcontrib>Jagannathan, B.</creatorcontrib><creatorcontrib>Narasimha, S.</creatorcontrib><creatorcontrib>Chou, A.</creatorcontrib><creatorcontrib>Zamdmer, N.</creatorcontrib><creatorcontrib>Johnson, J.</creatorcontrib><creatorcontrib>Williams, R.</creatorcontrib><creatorcontrib>Wagner, L.</creatorcontrib><creatorcontrib>Jonghae Kim</creatorcontrib><creatorcontrib>Plouchart, J.-O.</creatorcontrib><creatorcontrib>Pekarik, J.</creatorcontrib><creatorcontrib>Springer, S.</creatorcontrib><creatorcontrib>Freeman, G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sungjae Lee</au><au>Jagannathan, B.</au><au>Narasimha, S.</au><au>Chou, A.</au><au>Zamdmer, N.</au><au>Johnson, J.</au><au>Williams, R.</au><au>Wagner, L.</au><au>Jonghae Kim</au><au>Plouchart, J.-O.</au><au>Pekarik, J.</au><au>Springer, S.</au><au>Freeman, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Record RF performance of 45-nm SOI CMOS Technology</atitle><btitle>2007 IEEE International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2007-12</date><risdate>2007</risdate><spage>255</spage><epage>258</epage><pages>255-258</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>1424415071</isbn><isbn>9781424415076</isbn><eisbn>142441508X</eisbn><eisbn>9781424415083</eisbn><abstract>We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak f T 's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured f T 's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak f T of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2007.4418916</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0163-1918 |
| ispartof | 2007 IEEE International Electron Devices Meeting, 2007, p.255-258 |
| issn | 0163-1918 2156-017X |
| language | eng |
| recordid | cdi_ieee_primary_4418916 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance measurement CMOS technology FETs Insulation Leakage current Length measurement Parasitic capacitance Radio frequency Silicon on insulator technology Wiring |
| title | Record RF performance of 45-nm SOI CMOS Technology |
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