A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mistry, K., Chau, R., Choi, C.-H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Allen, C., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Auth, C., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Beattie, B., Prince, M., Ranade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Bergstrom, D., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K., Bost, M., Brazier, M., Buehler, M., Cappellani, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Copper Dual band High K dielectric materials High-K gate dielectrics Logic Manufacturing processes MOS devices Packaging Random access memory Silicon
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!