Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET

In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical equations. Taking into consideration the distribution of minority carriers in the silicon film, the analytic...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Zhang Zhengfan, Fang Jian, Li Ruzhang, Zhang Zhengyuan, Li Zhaoji
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Circuit simulation Equations Integrated circuit modeling Medical simulation MOS devices MOSFET circuits Semiconductor films Silicon Threshold voltage
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page	1157
container_issue
container_start_page	1154
container_title
container_volume
creator	Zhang Zhengfan Fang Jian Li Ruzhang Zhang Zhengyuan Li Zhaoji
description	In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical equations. Taking into consideration the distribution of minority carriers in the silicon film, the analytical threshold voltage model to make an accurate prediction of short-channel effect has been obtained, and also a further threshold voltage model including DIBL effect and interface charge effect was obtained. The analytical voltage model applies also to SOI NMOS devices. All of the above models have been verified by the results of 2D device simulator MEDICI.
doi_str_mv	10.1109/ICASIC.2007.4415838
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4415838</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4415838</ieee_id><sourcerecordid>4415838</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-d189eabd03294d11f73a3ba48fafe75752ccd8de9ffc52c037e2bd32be13e1b33</originalsourceid><addsrcrecordid>eNpFUMlqwzAUVDdomuYLctEPyNWT7Mg6FtPFkGKoU-gtSNaT46LEwUshf19DQ3uaDQZmCFkCjwC4fsizxzLPIsG5iuIYklSmF-QOYjEJkEJdkpmAlWAqST6v_gPQ139BDLdk0fdfnHPgSuuVmpH3za7DftcGR7_bMJga6b51GJpDTVtPHeKR9aPdN1XXHqhrRxuQ1WZA6scQTszhMeCAjpZFTt-K8vlpc09uvAk9Ls44Jx-Tm72ydfEyrVizBlQyMAepRmMdl0LHDsAraaQ1ceqNR5WoRFSVSx1q76uJc6lQWCeFRZAIVso5Wf72Noi4PXbN3nSn7fkb-QOTilUa</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Zhang Zhengfan ; Fang Jian ; Li Ruzhang ; Zhang Zhengyuan ; Li Zhaoji</creator><creatorcontrib>Zhang Zhengfan ; Fang Jian ; Li Ruzhang ; Zhang Zhengyuan ; Li Zhaoji</creatorcontrib><description>In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical equations. Taking into consideration the distribution of minority carriers in the silicon film, the analytical threshold voltage model to make an accurate prediction of short-channel effect has been obtained, and also a further threshold voltage model including DIBL effect and interface charge effect was obtained. The analytical voltage model applies also to SOI NMOS devices. All of the above models have been verified by the results of 2D device simulator MEDICI.</description><identifier>ISSN: 2162-7541</identifier><identifier>ISBN: 1424411319</identifier><identifier>ISBN: 9781424411313</identifier><identifier>EISSN: 2162-755X</identifier><identifier>EISBN: 1424411327</identifier><identifier>EISBN: 9781424411320</identifier><identifier>DOI: 10.1109/ICASIC.2007.4415838</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Circuit simulation ; Equations ; Integrated circuit modeling ; Medical simulation ; MOS devices ; MOSFET circuits ; Semiconductor films ; Silicon ; Threshold voltage</subject><ispartof>2007 7th International Conference on ASIC, 2007, p.1154-1157</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4415838$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27916,54911</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4415838$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhang Zhengfan</creatorcontrib><creatorcontrib>Fang Jian</creatorcontrib><creatorcontrib>Li Ruzhang</creatorcontrib><creatorcontrib>Zhang Zhengyuan</creatorcontrib><creatorcontrib>Li Zhaoji</creatorcontrib><title>Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET</title><title>2007 7th International Conference on ASIC</title><addtitle>ICASIC</addtitle><description>In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical equations. Taking into consideration the distribution of minority carriers in the silicon film, the analytical threshold voltage model to make an accurate prediction of short-channel effect has been obtained, and also a further threshold voltage model including DIBL effect and interface charge effect was obtained. The analytical voltage model applies also to SOI NMOS devices. All of the above models have been verified by the results of 2D device simulator MEDICI.</description><subject>Analytical models</subject><subject>Circuit simulation</subject><subject>Equations</subject><subject>Integrated circuit modeling</subject><subject>Medical simulation</subject><subject>MOS devices</subject><subject>MOSFET circuits</subject><subject>Semiconductor films</subject><subject>Silicon</subject><subject>Threshold voltage</subject><issn>2162-7541</issn><issn>2162-755X</issn><isbn>1424411319</isbn><isbn>9781424411313</isbn><isbn>1424411327</isbn><isbn>9781424411320</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUMlqwzAUVDdomuYLctEPyNWT7Mg6FtPFkGKoU-gtSNaT46LEwUshf19DQ3uaDQZmCFkCjwC4fsizxzLPIsG5iuIYklSmF-QOYjEJkEJdkpmAlWAqST6v_gPQ139BDLdk0fdfnHPgSuuVmpH3za7DftcGR7_bMJga6b51GJpDTVtPHeKR9aPdN1XXHqhrRxuQ1WZA6scQTszhMeCAjpZFTt-K8vlpc09uvAk9Ls44Jx-Tm72ydfEyrVizBlQyMAepRmMdl0LHDsAraaQ1ceqNR5WoRFSVSx1q76uJc6lQWCeFRZAIVso5Wf72Noi4PXbN3nSn7fkb-QOTilUa</recordid><startdate>200710</startdate><enddate>200710</enddate><creator>Zhang Zhengfan</creator><creator>Fang Jian</creator><creator>Li Ruzhang</creator><creator>Zhang Zhengyuan</creator><creator>Li Zhaoji</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200710</creationdate><title>Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET</title><author>Zhang Zhengfan ; Fang Jian ; Li Ruzhang ; Zhang Zhengyuan ; Li Zhaoji</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d189eabd03294d11f73a3ba48fafe75752ccd8de9ffc52c037e2bd32be13e1b33</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Analytical models</topic><topic>Circuit simulation</topic><topic>Equations</topic><topic>Integrated circuit modeling</topic><topic>Medical simulation</topic><topic>MOS devices</topic><topic>MOSFET circuits</topic><topic>Semiconductor films</topic><topic>Silicon</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Zhang Zhengfan</creatorcontrib><creatorcontrib>Fang Jian</creatorcontrib><creatorcontrib>Li Ruzhang</creatorcontrib><creatorcontrib>Zhang Zhengyuan</creatorcontrib><creatorcontrib>Li Zhaoji</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhang Zhengfan</au><au>Fang Jian</au><au>Li Ruzhang</au><au>Zhang Zhengyuan</au><au>Li Zhaoji</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET</atitle><btitle>2007 7th International Conference on ASIC</btitle><stitle>ICASIC</stitle><date>2007-10</date><risdate>2007</risdate><spage>1154</spage><epage>1157</epage><pages>1154-1157</pages><issn>2162-7541</issn><eissn>2162-755X</eissn><isbn>1424411319</isbn><isbn>9781424411313</isbn><eisbn>1424411327</eisbn><eisbn>9781424411320</eisbn><abstract>In this paper, the threshold voltage model using a quasi -2D approximation for deep submicron double-gate fully-depleted SOI PMOS devices was described by solving basic semiconductor physical equations. Taking into consideration the distribution of minority carriers in the silicon film, the analytical threshold voltage model to make an accurate prediction of short-channel effect has been obtained, and also a further threshold voltage model including DIBL effect and interface charge effect was obtained. The analytical voltage model applies also to SOI NMOS devices. All of the above models have been verified by the results of 2D device simulator MEDICI.</abstract><pub>IEEE</pub><doi>10.1109/ICASIC.2007.4415838</doi><tpages>4</tpages></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISSN: 2162-7541
ispartof	2007 7th International Conference on ASIC, 2007, p.1154-1157
issn	2162-7541 2162-755X
language	eng
recordid	cdi_ieee_primary_4415838
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Analytical models Circuit simulation Equations Integrated circuit modeling Medical simulation MOS devices MOSFET circuits Semiconductor films Silicon Threshold voltage
title	Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T22%3A45%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Threshold%20voltage%20modeling%20of%20deep-submicron%20double-gate%20fully-depleted%20SOI%20MOSFET&rft.btitle=2007%207th%20International%20Conference%20on%20ASIC&rft.au=Zhang%20Zhengfan&rft.date=2007-10&rft.spage=1154&rft.epage=1157&rft.pages=1154-1157&rft.issn=2162-7541&rft.eissn=2162-755X&rft.isbn=1424411319&rft.isbn_list=9781424411313&rft_id=info:doi/10.1109/ICASIC.2007.4415838&rft_dat=%3Cieee_6IE%3E4415838%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424411327&rft.eisbn_list=9781424411320&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4415838&rfr_iscdi=true