The research and design of reconfigurable cipher processing architecture targeted at block cipher
The design of a cipher processing system adopts reconfigurable computing technology, which can support multiple cryptographic algorithms in the cipher application. Therefore, it can achieve crypto algorithms processing with efficiency and flexibility, and it also solves the hidden trouble in the cip...
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| creator | Zi-Bin Dai Xiao-Hui Yang Qiao Ren Xue-Rong Yu |
| description | The design of a cipher processing system adopts reconfigurable computing technology, which can support multiple cryptographic algorithms in the cipher application. Therefore, it can achieve crypto algorithms processing with efficiency and flexibility, and it also solves the hidden trouble in the cipher processing system. This paper has analyzed processing structure characteristics of popular block cipher algorithms, and proposed a reconfigurable cipher processing architecture (RCPA) combining the design method of reconfigurable processing architecture. And a prototype has been implemented successfully based on RCPA. The prototype is realized using Altera's FPGA. Synthesis, placement and routing of RCPA have accomplished under 0.18 mum CMOS technology. The results prove that RCPA can achieve relatively high performance in block cipher algorithms processing. |
| doi_str_mv | 10.1109/ICASIC.2007.4415755 |
| format | Conference Proceeding |
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The results prove that RCPA can achieve relatively high performance in block cipher algorithms processing.</description><subject>Algorithm design and analysis</subject><subject>Block cipher</subject><subject>Computer architecture</subject><subject>Cryptography</subject><subject>Design methodology</subject><subject>Hardware</subject><subject>Parallel processing</subject><subject>Prototypes</subject><subject>RCPA</subject><subject>Reconfigurable</subject><subject>Reconfigurable architectures</subject><subject>Reconfigurable logic</subject><subject>VLIW</subject><issn>2162-7541</issn><issn>2162-755X</issn><isbn>1424411319</isbn><isbn>9781424411313</isbn><isbn>1424411327</isbn><isbn>9781424411320</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUEtOwzAUND-JUnqCbnyBlPf8iZMlqqBUqsSCIrGrHPslMZSkstMFtyeIClajmdGMNMPYHGGBCOXdenn_sl4uBIBZKIXaaH3GblCJkaAU5pxNBOYiG_W3i38Dy8s_Q-E1m6X0DgAIpixzM2F22xKPlMhG13Lbee4phabjfT3Kru_q0ByjrfbEXTi0FPkh9o5SCl3DfzJhIDccI_HBxoYG8twOvNr37uMUuGVXtd0nmp1wyl4fH7bLp2zzvBpHbbKARg9ZTkbKSou8glp5nUNRaAFOIaBGj8rkUtpCI6KVDslXntB6BFtW40pbyCmb__YGItodYvi08Wt3ukp-A3oQWbs</recordid><startdate>200710</startdate><enddate>200710</enddate><creator>Zi-Bin Dai</creator><creator>Xiao-Hui Yang</creator><creator>Qiao Ren</creator><creator>Xue-Rong Yu</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200710</creationdate><title>The research and design of reconfigurable cipher processing architecture targeted at block cipher</title><author>Zi-Bin Dai ; Xiao-Hui Yang ; Qiao Ren ; Xue-Rong Yu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-6e733b526b0f4d56088520c410151d147633a85111a3c1edbde1ad10a9b131a83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Algorithm design and analysis</topic><topic>Block cipher</topic><topic>Computer architecture</topic><topic>Cryptography</topic><topic>Design methodology</topic><topic>Hardware</topic><topic>Parallel processing</topic><topic>Prototypes</topic><topic>RCPA</topic><topic>Reconfigurable</topic><topic>Reconfigurable architectures</topic><topic>Reconfigurable logic</topic><topic>VLIW</topic><toplevel>online_resources</toplevel><creatorcontrib>Zi-Bin Dai</creatorcontrib><creatorcontrib>Xiao-Hui Yang</creatorcontrib><creatorcontrib>Qiao Ren</creatorcontrib><creatorcontrib>Xue-Rong Yu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zi-Bin Dai</au><au>Xiao-Hui Yang</au><au>Qiao Ren</au><au>Xue-Rong Yu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The research and design of reconfigurable cipher processing architecture targeted at block cipher</atitle><btitle>2007 7th International Conference on ASIC</btitle><stitle>ICASIC</stitle><date>2007-10</date><risdate>2007</risdate><spage>814</spage><epage>817</epage><pages>814-817</pages><issn>2162-7541</issn><eissn>2162-755X</eissn><isbn>1424411319</isbn><isbn>9781424411313</isbn><eisbn>1424411327</eisbn><eisbn>9781424411320</eisbn><abstract>The design of a cipher processing system adopts reconfigurable computing technology, which can support multiple cryptographic algorithms in the cipher application. Therefore, it can achieve crypto algorithms processing with efficiency and flexibility, and it also solves the hidden trouble in the cipher processing system. This paper has analyzed processing structure characteristics of popular block cipher algorithms, and proposed a reconfigurable cipher processing architecture (RCPA) combining the design method of reconfigurable processing architecture. And a prototype has been implemented successfully based on RCPA. The prototype is realized using Altera's FPGA. Synthesis, placement and routing of RCPA have accomplished under 0.18 mum CMOS technology. The results prove that RCPA can achieve relatively high performance in block cipher algorithms processing.</abstract><pub>IEEE</pub><doi>10.1109/ICASIC.2007.4415755</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2162-7541 |
| ispartof | 2007 7th International Conference on ASIC, 2007, p.814-817 |
| issn | 2162-7541 2162-755X |
| language | eng |
| recordid | cdi_ieee_primary_4415755 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Block cipher Computer architecture Cryptography Design methodology Hardware Parallel processing Prototypes RCPA Reconfigurable Reconfigurable architectures Reconfigurable logic VLIW |
| title | The research and design of reconfigurable cipher processing architecture targeted at block cipher |
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