Dynamic Data Stability in Low-power SRAM Design
SRAM cell stability measurement is traditionally based on static criteria of data stability requiring 3 coincident points in butterfly curves. We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the...
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| creator | Sharifkhani, M. Jahinuzzaman, S.M. Sachdev, M. |
| description | SRAM cell stability measurement is traditionally based on static criteria of data stability requiring 3 coincident points in butterfly curves. We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the cell can be made considerably higher than the SNM once the cell access time is sufficiently shorter than the cell time-constant. This behavior enables enhancing SRAM yield as well as reducing cell operating voltage without compromising reliability. A 40Kb SRAM designed using SVGND scheme exploits the dynamic behavior of the cell in order to increase the stability and reduce the static and dynamic power consumption. The SRAM unit realized in 0.13μm CMOS consumes 702μW at 100MHz during write operation and offers a 27pA/Cell leakage current. |
| doi_str_mv | 10.1109/CICC.2007.4405722 |
| format | Conference Proceeding |
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We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the cell can be made considerably higher than the SNM once the cell access time is sufficiently shorter than the cell time-constant. This behavior enables enhancing SRAM yield as well as reducing cell operating voltage without compromising reliability. A 40Kb SRAM designed using SVGND scheme exploits the dynamic behavior of the cell in order to increase the stability and reduce the static and dynamic power consumption. The SRAM unit realized in 0.13μm CMOS consumes 702μW at 100MHz during write operation and offers a 27pA/Cell leakage current.</abstract><pub>IEEE</pub><doi>10.1109/CICC.2007.4405722</doi><tpages>4</tpages></addata></record> |
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| ispartof | 2007 IEEE Custom Integrated Circuits Conference, 2007, p.237-240 |
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| language | eng |
| recordid | cdi_ieee_primary_4405722 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit noise Circuit stability Circuit testing Energy consumption Inverters Random access memory Stability criteria Variable structure systems Voltage Working environment noise |
| title | Dynamic Data Stability in Low-power SRAM Design |
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