Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan
Enhanced scan designs support high coverage TDF testing but with significant overhead. We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. Experimental results using commercial ATPG tools show that 60-90% of the...
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| creator | Gefu Xu Singh, A.D. |
| description | Enhanced scan designs support high coverage TDF testing but with significant overhead. We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. Experimental results using commercial ATPG tools show that 60-90% of the TDF coverage benefits of enhanced scan can be achieved at 10-30% of the cost. |
| doi_str_mv | 10.1109/ATS.2007.96 |
| format | Conference Proceeding |
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We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. 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We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. 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We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. Experimental results using commercial ATPG tools show that 60-90% of the TDF coverage benefits of enhanced scan can be achieved at 10-30% of the cost.</abstract><pub>IEEE</pub><doi>10.1109/ATS.2007.96</doi><tpages>6</tpages></addata></record> |
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| ispartof | 16th Asian Test Symposium (ATS 2007), 2007, p.335-340 |
| issn | 1081-7735 2377-5386 |
| language | eng |
| recordid | cdi_ieee_primary_4388035 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic test pattern generation Circuit testing Clocks Delay Flip-flops Logic testing Semiconductor device testing Stress Timing USA Councils |
| title | Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan |
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