The Region-Exhaustive Fault Model
Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 18 |
---|---|
container_issue | |
container_start_page | 13 |
container_title | |
container_volume | |
creator | Jas, A. Natarajan, S. Patil, S. |
description | Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models. |
doi_str_mv | 10.1109/ATS.2007.78 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4387976</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4387976</ieee_id><sourcerecordid>4387976</sourcerecordid><originalsourceid>FETCH-LOGICAL-i105t-4a145fa8c07eaae8794ac09a4e8b8c62ae990f3ddf09cda4fc4d23a93a702e3b3</originalsourceid><addsrcrecordid>eNotzE1Lw0AQgOHFD7DWnjx6iT9g4-zObmbnWEqrQkXQeC7TZGIj0UqTiv57C_pe3ttjzKWD3Dngm2n5nHsAyikdmZFHIhsxFcfmHKjg6BODPzEjB8lZIoxnZtL3b3AoRmLGkbkuN5o96Wu7_bDz743s-6H90mwh-27IHra1dhfmtJGu18n_x-ZlMS9nd3b5eHs_my5t6yAONogLsZFUAamIJuIgFbAETetUFV6UGRqs6wa4qiU0Vag9CqMQeMU1js3Vn9uq6upz177L7mcV8CBRgb-gzz87</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>The Region-Exhaustive Fault Model</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Jas, A. ; Natarajan, S. ; Patil, S.</creator><creatorcontrib>Jas, A. ; Natarajan, S. ; Patil, S.</creatorcontrib><description>Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.</description><identifier>ISSN: 1081-7735</identifier><identifier>ISBN: 0769528902</identifier><identifier>ISBN: 9780769528908</identifier><identifier>EISSN: 2377-5386</identifier><identifier>DOI: 10.1109/ATS.2007.78</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic test pattern generation ; Bridge circuits ; Circuit faults ; Circuit testing ; Failure analysis ; Fault detection ; Geometry ; Geophysical measurement techniques ; Ground penetrating radar ; Logic testing</subject><ispartof>16th Asian Test Symposium (ATS 2007), 2007, p.13-18</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4387976$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4387976$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jas, A.</creatorcontrib><creatorcontrib>Natarajan, S.</creatorcontrib><creatorcontrib>Patil, S.</creatorcontrib><title>The Region-Exhaustive Fault Model</title><title>16th Asian Test Symposium (ATS 2007)</title><addtitle>ATS</addtitle><description>Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.</description><subject>Automatic test pattern generation</subject><subject>Bridge circuits</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Failure analysis</subject><subject>Fault detection</subject><subject>Geometry</subject><subject>Geophysical measurement techniques</subject><subject>Ground penetrating radar</subject><subject>Logic testing</subject><issn>1081-7735</issn><issn>2377-5386</issn><isbn>0769528902</isbn><isbn>9780769528908</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzE1Lw0AQgOHFD7DWnjx6iT9g4-zObmbnWEqrQkXQeC7TZGIj0UqTiv57C_pe3ttjzKWD3Dngm2n5nHsAyikdmZFHIhsxFcfmHKjg6BODPzEjB8lZIoxnZtL3b3AoRmLGkbkuN5o96Wu7_bDz743s-6H90mwh-27IHra1dhfmtJGu18n_x-ZlMS9nd3b5eHs_my5t6yAONogLsZFUAamIJuIgFbAETetUFV6UGRqs6wa4qiU0Vag9CqMQeMU1js3Vn9uq6upz177L7mcV8CBRgb-gzz87</recordid><startdate>200710</startdate><enddate>200710</enddate><creator>Jas, A.</creator><creator>Natarajan, S.</creator><creator>Patil, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200710</creationdate><title>The Region-Exhaustive Fault Model</title><author>Jas, A. ; Natarajan, S. ; Patil, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i105t-4a145fa8c07eaae8794ac09a4e8b8c62ae990f3ddf09cda4fc4d23a93a702e3b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Automatic test pattern generation</topic><topic>Bridge circuits</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Failure analysis</topic><topic>Fault detection</topic><topic>Geometry</topic><topic>Geophysical measurement techniques</topic><topic>Ground penetrating radar</topic><topic>Logic testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Jas, A.</creatorcontrib><creatorcontrib>Natarajan, S.</creatorcontrib><creatorcontrib>Patil, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jas, A.</au><au>Natarajan, S.</au><au>Patil, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The Region-Exhaustive Fault Model</atitle><btitle>16th Asian Test Symposium (ATS 2007)</btitle><stitle>ATS</stitle><date>2007-10</date><risdate>2007</risdate><spage>13</spage><epage>18</epage><pages>13-18</pages><issn>1081-7735</issn><eissn>2377-5386</eissn><isbn>0769528902</isbn><isbn>9780769528908</isbn><abstract>Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.</abstract><pub>IEEE</pub><doi>10.1109/ATS.2007.78</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1081-7735 |
ispartof | 16th Asian Test Symposium (ATS 2007), 2007, p.13-18 |
issn | 1081-7735 2377-5386 |
language | eng |
recordid | cdi_ieee_primary_4387976 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Automatic test pattern generation Bridge circuits Circuit faults Circuit testing Failure analysis Fault detection Geometry Geophysical measurement techniques Ground penetrating radar Logic testing |
title | The Region-Exhaustive Fault Model |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T00%3A08%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=The%20Region-Exhaustive%20Fault%20Model&rft.btitle=16th%20Asian%20Test%20Symposium%20(ATS%202007)&rft.au=Jas,%20A.&rft.date=2007-10&rft.spage=13&rft.epage=18&rft.pages=13-18&rft.issn=1081-7735&rft.eissn=2377-5386&rft.isbn=0769528902&rft.isbn_list=9780769528908&rft_id=info:doi/10.1109/ATS.2007.78&rft_dat=%3Cieee_6IE%3E4387976%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4387976&rfr_iscdi=true |