Maintaining System Signal and Power Integrity Characteristics as Part of a Module Cost-Reduction Exercise

This paper describes design activity which involved replacing an existing ceramic single chip module package design with a new organic laminate version, each using the same ASIC, for the purpose of cost reduction, and subject to stringent system level design constraints. Since the electrical propert...

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Bibliographische Detailangaben

Hauptverfasser:	Dahlen, P.E., Timpane, T., Becker, D.J., Liang, T.W., Martin, W.D., Rudrud, P., Bartley, G.K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific integrated circuits ceramic package Ceramics Conducting materials Costs Delay Dielectric materials Laminates organic package Packaging power integrity Signal design signal integrity system timing Timing
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