A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)
The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel w...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 167 |
|---|---|
| container_issue | |
| container_start_page | 166 |
| container_title | |
| container_volume | |
| creator | Han, S.Y. Park, J.M. Sohn, S.O. Lee, J.B. Chae, K.S. Jeon, C.H. Park, J.S. Kim, S.D. Kim, W.J. Yamada, S. Kim, Y.P. Park, H.S. Cho, N.M. Kim, H.H. Lee, M.S. Lee, Y.S. Yang, W. Donggun Park Byung-il Ryu |
| description | The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology. |
| doi_str_mv | 10.1109/VLSIT.2007.4339768 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4339768</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4339768</ieee_id><sourcerecordid>4339768</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-d52791b53c91e7a641411bdec3349956dce34c2f82a54878f19ddd9fe76e931b3</originalsourceid><addsrcrecordid>eNotkDFPwzAYRC0BEm3hD8DikQ4udmzH8VgChUoFIlpYKzf-AgaTVLED6sRfJ1I73d3w3nAIXTA6YYzq67fFcr6aJJSqieBcqzQ7QkOh-50JytNjNKBKcMJkmpyiYQiflCZU8myA_qb4qfkBj29fpo84B-_xqjV1cCE2LZ6BiV3r6ndscGHa6Iz3O-Lq0HkTweKbzn_hmatndyt8VTiyr2P86-JHj2yNJUXjd8F5VzY1XjoLOG_qaMoYemCZj8_QSWV8gPNDjtBrb8gfyOL5fp5PF8QxJSOxMlGabSQvNQNlUsEEYxsLJedCa5naErgokypLjBSZyiqmrbW6ApWC5mzDR-hy73UAsN627tu0u_XhLP4PKMtdCw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Han, S.Y. ; Park, J.M. ; Sohn, S.O. ; Lee, J.B. ; Chae, K.S. ; Jeon, C.H. ; Park, J.S. ; Kim, S.D. ; Kim, W.J. ; Yamada, S. ; Kim, Y.P. ; Park, H.S. ; Cho, N.M. ; Kim, H.H. ; Lee, M.S. ; Lee, Y.S. ; Yang, W. ; Donggun Park ; Byung-il Ryu</creator><creatorcontrib>Han, S.Y. ; Park, J.M. ; Sohn, S.O. ; Lee, J.B. ; Chae, K.S. ; Jeon, C.H. ; Park, J.S. ; Kim, S.D. ; Kim, W.J. ; Yamada, S. ; Kim, Y.P. ; Park, H.S. ; Cho, N.M. ; Kim, H.H. ; Lee, M.S. ; Lee, Y.S. ; Yang, W. ; Donggun Park ; Byung-il Ryu</creatorcontrib><description>The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 4900784036</identifier><identifier>ISBN: 9784900784031</identifier><identifier>DOI: 10.1109/VLSIT.2007.4339768</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS technology ; Epitaxial growth ; FinFETs ; Hot carriers ; Insulation ; Leakage current ; Random access memory ; Research and development ; Silicon ; Transistors</subject><ispartof>2007 IEEE Symposium on VLSI Technology, 2007, p.166-167</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4339768$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4339768$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Han, S.Y.</creatorcontrib><creatorcontrib>Park, J.M.</creatorcontrib><creatorcontrib>Sohn, S.O.</creatorcontrib><creatorcontrib>Lee, J.B.</creatorcontrib><creatorcontrib>Chae, K.S.</creatorcontrib><creatorcontrib>Jeon, C.H.</creatorcontrib><creatorcontrib>Park, J.S.</creatorcontrib><creatorcontrib>Kim, S.D.</creatorcontrib><creatorcontrib>Kim, W.J.</creatorcontrib><creatorcontrib>Yamada, S.</creatorcontrib><creatorcontrib>Kim, Y.P.</creatorcontrib><creatorcontrib>Park, H.S.</creatorcontrib><creatorcontrib>Cho, N.M.</creatorcontrib><creatorcontrib>Kim, H.H.</creatorcontrib><creatorcontrib>Lee, M.S.</creatorcontrib><creatorcontrib>Lee, Y.S.</creatorcontrib><creatorcontrib>Yang, W.</creatorcontrib><creatorcontrib>Donggun Park</creatorcontrib><creatorcontrib>Byung-il Ryu</creatorcontrib><title>A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)</title><title>2007 IEEE Symposium on VLSI Technology</title><addtitle>VLSIT</addtitle><description>The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.</description><subject>CMOS technology</subject><subject>Epitaxial growth</subject><subject>FinFETs</subject><subject>Hot carriers</subject><subject>Insulation</subject><subject>Leakage current</subject><subject>Random access memory</subject><subject>Research and development</subject><subject>Silicon</subject><subject>Transistors</subject><issn>0743-1562</issn><isbn>4900784036</isbn><isbn>9784900784031</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkDFPwzAYRC0BEm3hD8DikQ4udmzH8VgChUoFIlpYKzf-AgaTVLED6sRfJ1I73d3w3nAIXTA6YYzq67fFcr6aJJSqieBcqzQ7QkOh-50JytNjNKBKcMJkmpyiYQiflCZU8myA_qb4qfkBj29fpo84B-_xqjV1cCE2LZ6BiV3r6ndscGHa6Iz3O-Lq0HkTweKbzn_hmatndyt8VTiyr2P86-JHj2yNJUXjd8F5VzY1XjoLOG_qaMoYemCZj8_QSWV8gPNDjtBrb8gfyOL5fp5PF8QxJSOxMlGabSQvNQNlUsEEYxsLJedCa5naErgokypLjBSZyiqmrbW6ApWC5mzDR-hy73UAsN627tu0u_XhLP4PKMtdCw</recordid><startdate>200706</startdate><enddate>200706</enddate><creator>Han, S.Y.</creator><creator>Park, J.M.</creator><creator>Sohn, S.O.</creator><creator>Lee, J.B.</creator><creator>Chae, K.S.</creator><creator>Jeon, C.H.</creator><creator>Park, J.S.</creator><creator>Kim, S.D.</creator><creator>Kim, W.J.</creator><creator>Yamada, S.</creator><creator>Kim, Y.P.</creator><creator>Park, H.S.</creator><creator>Cho, N.M.</creator><creator>Kim, H.H.</creator><creator>Lee, M.S.</creator><creator>Lee, Y.S.</creator><creator>Yang, W.</creator><creator>Donggun Park</creator><creator>Byung-il Ryu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200706</creationdate><title>A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)</title><author>Han, S.Y. ; Park, J.M. ; Sohn, S.O. ; Lee, J.B. ; Chae, K.S. ; Jeon, C.H. ; Park, J.S. ; Kim, S.D. ; Kim, W.J. ; Yamada, S. ; Kim, Y.P. ; Park, H.S. ; Cho, N.M. ; Kim, H.H. ; Lee, M.S. ; Lee, Y.S. ; Yang, W. ; Donggun Park ; Byung-il Ryu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d52791b53c91e7a641411bdec3349956dce34c2f82a54878f19ddd9fe76e931b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>CMOS technology</topic><topic>Epitaxial growth</topic><topic>FinFETs</topic><topic>Hot carriers</topic><topic>Insulation</topic><topic>Leakage current</topic><topic>Random access memory</topic><topic>Research and development</topic><topic>Silicon</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Han, S.Y.</creatorcontrib><creatorcontrib>Park, J.M.</creatorcontrib><creatorcontrib>Sohn, S.O.</creatorcontrib><creatorcontrib>Lee, J.B.</creatorcontrib><creatorcontrib>Chae, K.S.</creatorcontrib><creatorcontrib>Jeon, C.H.</creatorcontrib><creatorcontrib>Park, J.S.</creatorcontrib><creatorcontrib>Kim, S.D.</creatorcontrib><creatorcontrib>Kim, W.J.</creatorcontrib><creatorcontrib>Yamada, S.</creatorcontrib><creatorcontrib>Kim, Y.P.</creatorcontrib><creatorcontrib>Park, H.S.</creatorcontrib><creatorcontrib>Cho, N.M.</creatorcontrib><creatorcontrib>Kim, H.H.</creatorcontrib><creatorcontrib>Lee, M.S.</creatorcontrib><creatorcontrib>Lee, Y.S.</creatorcontrib><creatorcontrib>Yang, W.</creatorcontrib><creatorcontrib>Donggun Park</creatorcontrib><creatorcontrib>Byung-il Ryu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Han, S.Y.</au><au>Park, J.M.</au><au>Sohn, S.O.</au><au>Lee, J.B.</au><au>Chae, K.S.</au><au>Jeon, C.H.</au><au>Park, J.S.</au><au>Kim, S.D.</au><au>Kim, W.J.</au><au>Yamada, S.</au><au>Kim, Y.P.</au><au>Park, H.S.</au><au>Cho, N.M.</au><au>Kim, H.H.</au><au>Lee, M.S.</au><au>Lee, Y.S.</au><au>Yang, W.</au><au>Donggun Park</au><au>Byung-il Ryu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)</atitle><btitle>2007 IEEE Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2007-06</date><risdate>2007</risdate><spage>166</spage><epage>167</epage><pages>166-167</pages><issn>0743-1562</issn><isbn>4900784036</isbn><isbn>9784900784031</isbn><abstract>The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2007.4339768</doi><tpages>2</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0743-1562 |
| ispartof | 2007 IEEE Symposium on VLSI Technology, 2007, p.166-167 |
| issn | 0743-1562 |
| language | eng |
| recordid | cdi_ieee_primary_4339768 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS technology Epitaxial growth FinFETs Hot carriers Insulation Leakage current Random access memory Research and development Silicon Transistors |
| title | A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC) |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T06%3A53%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Novel%20DRAM%20Cell%20Transistor%20Featuring%20a%20Partially-insulated%20Bulk%20FinFET%20(Pi-FinFET)%20with%20a%20pad-Polysilicon%20Side%20Contacts%20(PSC)&rft.btitle=2007%20IEEE%20Symposium%20on%20VLSI%20Technology&rft.au=Han,%20S.Y.&rft.date=2007-06&rft.spage=166&rft.epage=167&rft.pages=166-167&rft.issn=0743-1562&rft.isbn=4900784036&rft.isbn_list=9784900784031&rft_id=info:doi/10.1109/VLSIT.2007.4339768&rft_dat=%3Cieee_6IE%3E4339768%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4339768&rfr_iscdi=true |