Multiple Stress Memorization In Advanced SOI CMOS Technologies
Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent...
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| creator | Wei, A. Wiatr, M. Mowry, A. Gehring, A. Boschke, R. Scott, C. Hoentschel, J. Duenkel, S. Gerhardt, M. Feudel, T. Lenski, M. Wirbeleit, F. Otterbach, R. Callahan, R. Koerner, G. Krumm, N. Greenlaw, D. Raab, M. Horstmann, M. |
| description | Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing. |
| doi_str_mv | 10.1109/VLSIT.2007.4339698 |
| format | Conference Proceeding |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS technology Paper technology Stress Very large scale integration |
| title | Multiple Stress Memorization In Advanced SOI CMOS Technologies |
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