Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform

We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V d =1.2 V are 0.54 mA/um at I off =40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I perfor...

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Hauptverfasser:	Sukegawa, K., Shimoda, Y., Tajima, M., Oryoji, M., Nakata, Y., Watatani, H., Sakai, H., Asneil, A., Sakai, S., Matsuyama, H., Kurata, H., Yamamoto, T., Tsukune, A., Shimizu, N., Futatsugi, T., Satoh, S., Kase, M., Sugii, T., Kudo, H., Kubo, T., Sukegawa, T., Ehara, H., Ochmizu, H., Fukuda, M., Mizushima, Y.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Annealing Bonding Delay Dielectrics Leakage current MOS devices Plasma chemistry Thermal stresses Wire Wiring
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