Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform
We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V d =1.2 V are 0.54 mA/um at I off =40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I perfor...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 175 |
|---|---|
| container_issue | |
| container_start_page | 174 |
| container_title | |
| container_volume | |
| creator | Sukegawa, K. Shimoda, Y. Tajima, M. Oryoji, M. Nakata, Y. Watatani, H. Sakai, H. Asneil, A. Sakai, S. Matsuyama, H. Kurata, H. Yamamoto, T. Tsukune, A. Shimizu, N. Futatsugi, T. Satoh, S. Kase, M. Sugii, T. Kudo, H. Kubo, T. Sukegawa, T. Ehara, H. Ochmizu, H. Fukuda, M. Mizushima, Y. |
| description | We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V d =1.2 V are 0.54 mA/um at I off =40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding. |
| doi_str_mv | 10.1109/VLSIT.2007.4339681 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4339681</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4339681</ieee_id><sourcerecordid>4339681</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-485f481b850402a0911e0c96a1c1c75e93f78336b31180c34b56f98a2a554a73</originalsourceid><addsrcrecordid>eNotkNFKwzAYhQMquE1fQG_yAt3-NEmbXMp0WihYWPF2_M3SUdclI8kQ394xd3E4nI_DuTiEPDGYMwZ68VWvq3aeA5RzwbkuFLshU6HPWQngxS2ZQCl4xmSR35NpjN8AOUiuJiS92qN1W-xGSyuX7C5gGryjvqer0zhmjQ_-FGntf7L9pRCMd86aRNFtL3i0uMedXVyC8THRNqCLQ0w-0P4sId2B1uu2oc2I6UwOD-SuxzHax6vPSLt6a5cfWf35Xi1f6mxgpUyZULIXinVKgoAcQTNmwegCmWGmlFbzvlScFx1nTIHhopNFrxXmKKXAks_I8__sYK3dHMNwwPC7uR7E_wCipVmr</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Sukegawa, K. ; Shimoda, Y. ; Tajima, M. ; Oryoji, M. ; Nakata, Y. ; Watatani, H. ; Sakai, H. ; Asneil, A. ; Sakai, S. ; Matsuyama, H. ; Kurata, H. ; Yamamoto, T. ; Tsukune, A. ; Shimizu, N. ; Futatsugi, T. ; Satoh, S. ; Kase, M. ; Sugii, T. ; Kudo, H. ; Kubo, T. ; Sukegawa, T. ; Ehara, H. ; Ochmizu, H. ; Fukuda, M. ; Mizushima, Y.</creator><creatorcontrib>Sukegawa, K. ; Shimoda, Y. ; Tajima, M. ; Oryoji, M. ; Nakata, Y. ; Watatani, H. ; Sakai, H. ; Asneil, A. ; Sakai, S. ; Matsuyama, H. ; Kurata, H. ; Yamamoto, T. ; Tsukune, A. ; Shimizu, N. ; Futatsugi, T. ; Satoh, S. ; Kase, M. ; Sugii, T. ; Kudo, H. ; Kubo, T. ; Sukegawa, T. ; Ehara, H. ; Ochmizu, H. ; Fukuda, M. ; Mizushima, Y.</creatorcontrib><description>We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V d =1.2 V are 0.54 mA/um at I off =40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 4900784036</identifier><identifier>ISBN: 9784900784031</identifier><identifier>DOI: 10.1109/VLSIT.2007.4339681</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Bonding ; Delay ; Dielectrics ; Leakage current ; MOS devices ; Plasma chemistry ; Thermal stresses ; Wire ; Wiring</subject><ispartof>2007 IEEE Symposium on VLSI Technology, 2007, p.174-175</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4339681$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4339681$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sukegawa, K.</creatorcontrib><creatorcontrib>Shimoda, Y.</creatorcontrib><creatorcontrib>Tajima, M.</creatorcontrib><creatorcontrib>Oryoji, M.</creatorcontrib><creatorcontrib>Nakata, Y.</creatorcontrib><creatorcontrib>Watatani, H.</creatorcontrib><creatorcontrib>Sakai, H.</creatorcontrib><creatorcontrib>Asneil, A.</creatorcontrib><creatorcontrib>Sakai, S.</creatorcontrib><creatorcontrib>Matsuyama, H.</creatorcontrib><creatorcontrib>Kurata, H.</creatorcontrib><creatorcontrib>Yamamoto, T.</creatorcontrib><creatorcontrib>Tsukune, A.</creatorcontrib><creatorcontrib>Shimizu, N.</creatorcontrib><creatorcontrib>Futatsugi, T.</creatorcontrib><creatorcontrib>Satoh, S.</creatorcontrib><creatorcontrib>Kase, M.</creatorcontrib><creatorcontrib>Sugii, T.</creatorcontrib><creatorcontrib>Kudo, H.</creatorcontrib><creatorcontrib>Kubo, T.</creatorcontrib><creatorcontrib>Sukegawa, T.</creatorcontrib><creatorcontrib>Ehara, H.</creatorcontrib><creatorcontrib>Ochmizu, H.</creatorcontrib><creatorcontrib>Fukuda, M.</creatorcontrib><creatorcontrib>Mizushima, Y.</creatorcontrib><title>Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform</title><title>2007 IEEE Symposium on VLSI Technology</title><addtitle>VLSIT</addtitle><description>We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V d =1.2 V are 0.54 mA/um at I off =40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding.</description><subject>Annealing</subject><subject>Bonding</subject><subject>Delay</subject><subject>Dielectrics</subject><subject>Leakage current</subject><subject>MOS devices</subject><subject>Plasma chemistry</subject><subject>Thermal stresses</subject><subject>Wire</subject><subject>Wiring</subject><issn>0743-1562</issn><isbn>4900784036</isbn><isbn>9784900784031</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkNFKwzAYhQMquE1fQG_yAt3-NEmbXMp0WihYWPF2_M3SUdclI8kQ394xd3E4nI_DuTiEPDGYMwZ68VWvq3aeA5RzwbkuFLshU6HPWQngxS2ZQCl4xmSR35NpjN8AOUiuJiS92qN1W-xGSyuX7C5gGryjvqer0zhmjQ_-FGntf7L9pRCMd86aRNFtL3i0uMedXVyC8THRNqCLQ0w-0P4sId2B1uu2oc2I6UwOD-SuxzHax6vPSLt6a5cfWf35Xi1f6mxgpUyZULIXinVKgoAcQTNmwegCmWGmlFbzvlScFx1nTIHhopNFrxXmKKXAks_I8__sYK3dHMNwwPC7uR7E_wCipVmr</recordid><startdate>200706</startdate><enddate>200706</enddate><creator>Sukegawa, K.</creator><creator>Shimoda, Y.</creator><creator>Tajima, M.</creator><creator>Oryoji, M.</creator><creator>Nakata, Y.</creator><creator>Watatani, H.</creator><creator>Sakai, H.</creator><creator>Asneil, A.</creator><creator>Sakai, S.</creator><creator>Matsuyama, H.</creator><creator>Kurata, H.</creator><creator>Yamamoto, T.</creator><creator>Tsukune, A.</creator><creator>Shimizu, N.</creator><creator>Futatsugi, T.</creator><creator>Satoh, S.</creator><creator>Kase, M.</creator><creator>Sugii, T.</creator><creator>Kudo, H.</creator><creator>Kubo, T.</creator><creator>Sukegawa, T.</creator><creator>Ehara, H.</creator><creator>Ochmizu, H.</creator><creator>Fukuda, M.</creator><creator>Mizushima, Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200706</creationdate><title>Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform</title><author>Sukegawa, K. ; Shimoda, Y. ; Tajima, M. ; Oryoji, M. ; Nakata, Y. ; Watatani, H. ; Sakai, H. ; Asneil, A. ; Sakai, S. ; Matsuyama, H. ; Kurata, H. ; Yamamoto, T. ; Tsukune, A. ; Shimizu, N. ; Futatsugi, T. ; Satoh, S. ; Kase, M. ; Sugii, T. ; Kudo, H. ; Kubo, T. ; Sukegawa, T. ; Ehara, H. ; Ochmizu, H. ; Fukuda, M. ; Mizushima, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-485f481b850402a0911e0c96a1c1c75e93f78336b31180c34b56f98a2a554a73</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Annealing</topic><topic>Bonding</topic><topic>Delay</topic><topic>Dielectrics</topic><topic>Leakage current</topic><topic>MOS devices</topic><topic>Plasma chemistry</topic><topic>Thermal stresses</topic><topic>Wire</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Sukegawa, K.</creatorcontrib><creatorcontrib>Shimoda, Y.</creatorcontrib><creatorcontrib>Tajima, M.</creatorcontrib><creatorcontrib>Oryoji, M.</creatorcontrib><creatorcontrib>Nakata, Y.</creatorcontrib><creatorcontrib>Watatani, H.</creatorcontrib><creatorcontrib>Sakai, H.</creatorcontrib><creatorcontrib>Asneil, A.</creatorcontrib><creatorcontrib>Sakai, S.</creatorcontrib><creatorcontrib>Matsuyama, H.</creatorcontrib><creatorcontrib>Kurata, H.</creatorcontrib><creatorcontrib>Yamamoto, T.</creatorcontrib><creatorcontrib>Tsukune, A.</creatorcontrib><creatorcontrib>Shimizu, N.</creatorcontrib><creatorcontrib>Futatsugi, T.</creatorcontrib><creatorcontrib>Satoh, S.</creatorcontrib><creatorcontrib>Kase, M.</creatorcontrib><creatorcontrib>Sugii, T.</creatorcontrib><creatorcontrib>Kudo, H.</creatorcontrib><creatorcontrib>Kubo, T.</creatorcontrib><creatorcontrib>Sukegawa, T.</creatorcontrib><creatorcontrib>Ehara, H.</creatorcontrib><creatorcontrib>Ochmizu, H.</creatorcontrib><creatorcontrib>Fukuda, M.</creatorcontrib><creatorcontrib>Mizushima, Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sukegawa, K.</au><au>Shimoda, Y.</au><au>Tajima, M.</au><au>Oryoji, M.</au><au>Nakata, Y.</au><au>Watatani, H.</au><au>Sakai, H.</au><au>Asneil, A.</au><au>Sakai, S.</au><au>Matsuyama, H.</au><au>Kurata, H.</au><au>Yamamoto, T.</au><au>Tsukune, A.</au><au>Shimizu, N.</au><au>Futatsugi, T.</au><au>Satoh, S.</au><au>Kase, M.</au><au>Sugii, T.</au><au>Kudo, H.</au><au>Kubo, T.</au><au>Sukegawa, T.</au><au>Ehara, H.</au><au>Ochmizu, H.</au><au>Fukuda, M.</au><au>Mizushima, Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform</atitle><btitle>2007 IEEE Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2007-06</date><risdate>2007</risdate><spage>174</spage><epage>175</epage><pages>174-175</pages><issn>0743-1562</issn><isbn>4900784036</isbn><isbn>9784900784031</isbn><abstract>We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V d =1.2 V are 0.54 mA/um at I off =40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2007.4339681</doi><tpages>2</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0743-1562 |
| ispartof | 2007 IEEE Symposium on VLSI Technology, 2007, p.174-175 |
| issn | 0743-1562 |
| language | eng |
| recordid | cdi_ieee_primary_4339681 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Annealing Bonding Delay Dielectrics Leakage current MOS devices Plasma chemistry Thermal stresses Wire Wiring |
| title | Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T14%3A39%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Dependable%20Integration%20of%20Full-Porous%20Low-k%20Interconnect%20and%20Low-leakage/%20Low-cost%20Transistor%20for%2045nm%20LSTP%20Platform&rft.btitle=2007%20IEEE%20Symposium%20on%20VLSI%20Technology&rft.au=Sukegawa,%20K.&rft.date=2007-06&rft.spage=174&rft.epage=175&rft.pages=174-175&rft.issn=0743-1562&rft.isbn=4900784036&rft.isbn_list=9784900784031&rft_id=info:doi/10.1109/VLSIT.2007.4339681&rft_dat=%3Cieee_6IE%3E4339681%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4339681&rfr_iscdi=true |