Low Temperature Performance of Deep Submicron Germanium pMOSFETs
The electrical characteristics of germanium (Ge) pMOSFETs with high-κ dielectric and gate lengths down to 125nm have been studied as a function of temperature down to 77K. The effective hole mobility improves from 235cm2/Vs at room temperature to 490cm2/Vs at 77K due to the reduction of phonon scatt...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 65 |
---|---|
container_issue | |
container_start_page | 62 |
container_title | |
container_volume | |
creator | Dobbie, Andy Nicholas, Gareth Meuris, Marc Parker, Evan H. C. Whall, Terry E. |
description | The electrical characteristics of germanium (Ge) pMOSFETs with high-κ dielectric and gate lengths down to 125nm have been studied as a function of temperature down to 77K. The effective hole mobility improves from 235cm2/Vs at room temperature to 490cm2/Vs at 77K due to the reduction of phonon scattering. We report a drive current enhancement of 1001 μA/μm at 295K to 1394μA/μm at 77K for L = 125nm and VG - VT = VD = -1.5V and a reduction in the off-current by 1-2 decades. The decrease in the subthreshold slope from 100mV/dec to 37mV/dec at 77K would allow power supply voltage scaling, further reducing the off-state current, and making Ge transistors suitable candidates for low temperature CMOS applications. |
doi_str_mv | 10.1109/EDST.2007.4289778 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4289778</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4289778</ieee_id><sourcerecordid>4289778</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-da93892019826159b80ba9d72babdeaf1f6a1daec6c44655e5a022ec93922e33</originalsourceid><addsrcrecordid>eNo1j91KxDAQhSMiqGsfQLzJC7RO0qTJ3Cn7p1BZob1fpu0UKnZb0i3i27vievVxzgcHjhD3ChKlAB_Xq6JMNIBLjPbonL8QETqvjDbm5D1eitv_4Oy1iKbpAwCUywwYfyOe8uFLltyPHOg4B5bvHNoh9HSoWQ6tXDGPspirvqvDcJBb_lXd3MvxbVds1uV0J65a-pw4OnMhylO9fInz3fZ1-ZzHnXL2GDeEqUcNCr3OlMXKQ0XYOF1R1TC1qs1INcR1VhuTWcuWQGuuMcUT0nQhHv5mO2bej6HrKXzvz5_THz2cSdI</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Low Temperature Performance of Deep Submicron Germanium pMOSFETs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Dobbie, Andy ; Nicholas, Gareth ; Meuris, Marc ; Parker, Evan H. C. ; Whall, Terry E.</creator><creatorcontrib>Dobbie, Andy ; Nicholas, Gareth ; Meuris, Marc ; Parker, Evan H. C. ; Whall, Terry E.</creatorcontrib><description>The electrical characteristics of germanium (Ge) pMOSFETs with high-κ dielectric and gate lengths down to 125nm have been studied as a function of temperature down to 77K. The effective hole mobility improves from 235cm2/Vs at room temperature to 490cm2/Vs at 77K due to the reduction of phonon scattering. We report a drive current enhancement of 1001 μA/μm at 295K to 1394μA/μm at 77K for L = 125nm and VG - VT = VD = -1.5V and a reduction in the off-current by 1-2 decades. The decrease in the subthreshold slope from 100mV/dec to 37mV/dec at 77K would allow power supply voltage scaling, further reducing the off-state current, and making Ge transistors suitable candidates for low temperature CMOS applications.</description><identifier>ISBN: 1424410975</identifier><identifier>ISBN: 9781424410972</identifier><identifier>EISBN: 9781424410989</identifier><identifier>EISBN: 1424410983</identifier><identifier>DOI: 10.1109/EDST.2007.4289778</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Capacitance-voltage characteristics ; cryogenic temperatures ; Cryogenics ; Germanium ; Germanium (Ge) ; high-k ; High-K gate dielectrics ; Implants ; MOSFETs ; Optical scattering ; Silicon ; Temperature</subject><ispartof>2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007, p.62-65</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4289778$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4289778$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Dobbie, Andy</creatorcontrib><creatorcontrib>Nicholas, Gareth</creatorcontrib><creatorcontrib>Meuris, Marc</creatorcontrib><creatorcontrib>Parker, Evan H. C.</creatorcontrib><creatorcontrib>Whall, Terry E.</creatorcontrib><title>Low Temperature Performance of Deep Submicron Germanium pMOSFETs</title><title>2007 International Workshop on Electron Devices and Semiconductor Technology (EDST)</title><addtitle>EDST</addtitle><description>The electrical characteristics of germanium (Ge) pMOSFETs with high-κ dielectric and gate lengths down to 125nm have been studied as a function of temperature down to 77K. The effective hole mobility improves from 235cm2/Vs at room temperature to 490cm2/Vs at 77K due to the reduction of phonon scattering. We report a drive current enhancement of 1001 μA/μm at 295K to 1394μA/μm at 77K for L = 125nm and VG - VT = VD = -1.5V and a reduction in the off-current by 1-2 decades. The decrease in the subthreshold slope from 100mV/dec to 37mV/dec at 77K would allow power supply voltage scaling, further reducing the off-state current, and making Ge transistors suitable candidates for low temperature CMOS applications.</description><subject>Annealing</subject><subject>Capacitance-voltage characteristics</subject><subject>cryogenic temperatures</subject><subject>Cryogenics</subject><subject>Germanium</subject><subject>Germanium (Ge)</subject><subject>high-k</subject><subject>High-K gate dielectrics</subject><subject>Implants</subject><subject>MOSFETs</subject><subject>Optical scattering</subject><subject>Silicon</subject><subject>Temperature</subject><isbn>1424410975</isbn><isbn>9781424410972</isbn><isbn>9781424410989</isbn><isbn>1424410983</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j91KxDAQhSMiqGsfQLzJC7RO0qTJ3Cn7p1BZob1fpu0UKnZb0i3i27vievVxzgcHjhD3ChKlAB_Xq6JMNIBLjPbonL8QETqvjDbm5D1eitv_4Oy1iKbpAwCUywwYfyOe8uFLltyPHOg4B5bvHNoh9HSoWQ6tXDGPspirvqvDcJBb_lXd3MvxbVds1uV0J65a-pw4OnMhylO9fInz3fZ1-ZzHnXL2GDeEqUcNCr3OlMXKQ0XYOF1R1TC1qs1INcR1VhuTWcuWQGuuMcUT0nQhHv5mO2bej6HrKXzvz5_THz2cSdI</recordid><startdate>200706</startdate><enddate>200706</enddate><creator>Dobbie, Andy</creator><creator>Nicholas, Gareth</creator><creator>Meuris, Marc</creator><creator>Parker, Evan H. C.</creator><creator>Whall, Terry E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200706</creationdate><title>Low Temperature Performance of Deep Submicron Germanium pMOSFETs</title><author>Dobbie, Andy ; Nicholas, Gareth ; Meuris, Marc ; Parker, Evan H. C. ; Whall, Terry E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-da93892019826159b80ba9d72babdeaf1f6a1daec6c44655e5a022ec93922e33</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Annealing</topic><topic>Capacitance-voltage characteristics</topic><topic>cryogenic temperatures</topic><topic>Cryogenics</topic><topic>Germanium</topic><topic>Germanium (Ge)</topic><topic>high-k</topic><topic>High-K gate dielectrics</topic><topic>Implants</topic><topic>MOSFETs</topic><topic>Optical scattering</topic><topic>Silicon</topic><topic>Temperature</topic><toplevel>online_resources</toplevel><creatorcontrib>Dobbie, Andy</creatorcontrib><creatorcontrib>Nicholas, Gareth</creatorcontrib><creatorcontrib>Meuris, Marc</creatorcontrib><creatorcontrib>Parker, Evan H. C.</creatorcontrib><creatorcontrib>Whall, Terry E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dobbie, Andy</au><au>Nicholas, Gareth</au><au>Meuris, Marc</au><au>Parker, Evan H. C.</au><au>Whall, Terry E.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low Temperature Performance of Deep Submicron Germanium pMOSFETs</atitle><btitle>2007 International Workshop on Electron Devices and Semiconductor Technology (EDST)</btitle><stitle>EDST</stitle><date>2007-06</date><risdate>2007</risdate><spage>62</spage><epage>65</epage><pages>62-65</pages><isbn>1424410975</isbn><isbn>9781424410972</isbn><eisbn>9781424410989</eisbn><eisbn>1424410983</eisbn><abstract>The electrical characteristics of germanium (Ge) pMOSFETs with high-κ dielectric and gate lengths down to 125nm have been studied as a function of temperature down to 77K. The effective hole mobility improves from 235cm2/Vs at room temperature to 490cm2/Vs at 77K due to the reduction of phonon scattering. We report a drive current enhancement of 1001 μA/μm at 295K to 1394μA/μm at 77K for L = 125nm and VG - VT = VD = -1.5V and a reduction in the off-current by 1-2 decades. The decrease in the subthreshold slope from 100mV/dec to 37mV/dec at 77K would allow power supply voltage scaling, further reducing the off-state current, and making Ge transistors suitable candidates for low temperature CMOS applications.</abstract><pub>IEEE</pub><doi>10.1109/EDST.2007.4289778</doi><tpages>4</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISBN: 1424410975 |
ispartof | 2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007, p.62-65 |
issn | |
language | eng |
recordid | cdi_ieee_primary_4289778 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Annealing Capacitance-voltage characteristics cryogenic temperatures Cryogenics Germanium Germanium (Ge) high-k High-K gate dielectrics Implants MOSFETs Optical scattering Silicon Temperature |
title | Low Temperature Performance of Deep Submicron Germanium pMOSFETs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-20T20%3A42%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Low%20Temperature%20Performance%20of%20Deep%20Submicron%20Germanium%20pMOSFETs&rft.btitle=2007%20International%20Workshop%20on%20Electron%20Devices%20and%20Semiconductor%20Technology%20(EDST)&rft.au=Dobbie,%20Andy&rft.date=2007-06&rft.spage=62&rft.epage=65&rft.pages=62-65&rft.isbn=1424410975&rft.isbn_list=9781424410972&rft_id=info:doi/10.1109/EDST.2007.4289778&rft_dat=%3Cieee_6IE%3E4289778%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424410989&rft.eisbn_list=1424410983&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4289778&rfr_iscdi=true |