The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors
We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results i...
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| creator | Lopez, G. Murali, R. Sarvari, R. Bowman, K. Davis, J. Meindl, J. |
| description | We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results indicate LER amplitudes start to become a substantial percentage of the nominal effective line-width dimension (2016 to 2020), leading to an increase in the conductor resistivity. Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture - as much as a 35% reduction for the maximum critical path delay mean degradation and standard deviation is observed for the year 2020 with a 14 nm half-pitch. |
| doi_str_mv | 10.1109/IITC.2007.382346 |
| format | Conference Proceeding |
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Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture - as much as a 35% reduction for the maximum critical path delay mean degradation and standard deviation is observed for the year 2020 with a 14 nm half-pitch.</description><subject>Computational modeling</subject><subject>Conductivity</subject><subject>Conductors</subject><subject>Copper</subject><subject>Delay effects</subject><subject>Electrons</subject><subject>Integrated circuit interconnections</subject><subject>Microprocessors</subject><subject>Rough surfaces</subject><subject>Surface roughness</subject><issn>2380-632X</issn><issn>2380-6338</issn><isbn>9781424410699</isbn><isbn>142441069X</isbn><isbn>1424410703</isbn><isbn>9781424410705</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9zN9KwzAUx_H4D5xz94I3eYHOJCdtk0upUwsbDpzi3ciaxEXapqQZON_CN7Y48dyciy-_D0JXlEwpJfKmLFfFlBGST0Ew4NkRuqCccU5JTuAYjRgIkmQA4gRNZC7-Wibl6X9jb-do0vcfZDiQKfB0hL5XW4PLplNVxN7iZ_dl8MxaU8Ueq1bjwnedCbhsowmVb9sh4GXwlel7_KqCU9H5tse-xXGAFurTNbsGF8FFV6kaL1Xc4jtTq_1Bb99r8-sudnV0SeHDMHJV8N3B9KG_RGdW1b2Z_P0xermfrYrHZP70UBa388TRPI2J5Ra0JRoyLYEroOlGEqEIUKJFrnkuKWPUpvlGccuVEZLqzHIgnGuwtIIxuj64zhiz7oJrVNivOcsgSwX8AHXuapk</recordid><startdate>200706</startdate><enddate>200706</enddate><creator>Lopez, G.</creator><creator>Murali, R.</creator><creator>Sarvari, R.</creator><creator>Bowman, K.</creator><creator>Davis, J.</creator><creator>Meindl, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200706</creationdate><title>The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors</title><author>Lopez, G. ; Murali, R. ; Sarvari, R. ; Bowman, K. ; Davis, J. ; Meindl, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f4f3df0d36d934a315b908a0310d87d4791221f57ba4f4ae891d6f43044d3f1c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Computational modeling</topic><topic>Conductivity</topic><topic>Conductors</topic><topic>Copper</topic><topic>Delay effects</topic><topic>Electrons</topic><topic>Integrated circuit interconnections</topic><topic>Microprocessors</topic><topic>Rough surfaces</topic><topic>Surface roughness</topic><toplevel>online_resources</toplevel><creatorcontrib>Lopez, G.</creatorcontrib><creatorcontrib>Murali, R.</creatorcontrib><creatorcontrib>Sarvari, R.</creatorcontrib><creatorcontrib>Bowman, K.</creatorcontrib><creatorcontrib>Davis, J.</creatorcontrib><creatorcontrib>Meindl, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lopez, G.</au><au>Murali, R.</au><au>Sarvari, R.</au><au>Bowman, K.</au><au>Davis, J.</au><au>Meindl, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors</atitle><btitle>2007 IEEE International Interconnect Technology Conferencee</btitle><stitle>IITC</stitle><date>2007-06</date><risdate>2007</risdate><spage>40</spage><epage>42</epage><pages>40-42</pages><issn>2380-632X</issn><eissn>2380-6338</eissn><isbn>9781424410699</isbn><isbn>142441069X</isbn><eisbn>1424410703</eisbn><eisbn>9781424410705</eisbn><abstract>We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results indicate LER amplitudes start to become a substantial percentage of the nominal effective line-width dimension (2016 to 2020), leading to an increase in the conductor resistivity. Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture - as much as a 35% reduction for the maximum critical path delay mean degradation and standard deviation is observed for the year 2020 with a 14 nm half-pitch.</abstract><pub>IEEE</pub><doi>10.1109/IITC.2007.382346</doi><tpages>3</tpages></addata></record> |
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| ispartof | 2007 IEEE International Interconnect Technology Conferencee, 2007, p.40-42 |
| issn | 2380-632X 2380-6338 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computational modeling Conductivity Conductors Copper Delay effects Electrons Integrated circuit interconnections Microprocessors Rough surfaces Surface roughness |
| title | The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors |
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