A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

A low power PRAM using a data-comparison write (DCW) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. At first, the DCW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with 128×8bits is implemented with a 0.8μm CMOS technology with a 0.5μm GST cell.