Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

This paper presents a new 32-bit adder structure with 12 GHz low-power operation in 65nm technology. The Fast Conditional Sparse-Tree Logic (FCSL) is based on modifying the initial Sparse-Tree architecture [1] to enhance its speed using tertiary trees and applying a carry-select scheme in some of th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Agah, Amir, Fakhraie, S. Mehdi, Emami-Neyestanak, Azita
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Circuit simulation Clocks Delay Frequency Logic circuits Merging Power dissipation Signal generators Wiring
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