PoP (Package-on-Package) Stacking Yield Loss Study

BGA package warpage during reflow soldering can cause open solder joint failure and in PoP case it's more critical to top joint (package-package interface) than to bottom joint (package-motherboard interface), as far as the former uses conventional flux dipping for SMT and the latter uses paste-printing. Design guideline for PoP reflow warpage was proposed based on the discussion of solder joint collapse at reflow. In order to avoid stacking failure of top joint, package reflow warpage defined on whole substrate should be less than 72 μm for 0.65 mm top pitch and 66 μm for 0.5 mm top pitch over solder liquidus temperature. Monte Carlo simulation study shows PoP stacking yield is sensitive to dimensional variations of package reflow warpage and bottom package top-pad size, and small change in those dimensions can create large stacking yield loss.