A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18mum CMO...

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Hauptverfasser: Kwak, Young-Ho, Jung, Inhwa, Lee, Hyung-Dong, Choi, Young-Jung, Kumar, Yogendera, Kim, Chulwoo
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Crosstalk
Delay
Detectors
Driver circuits
Inverters
Open loop systems
Phase locked loops
Signal generators
Voltage control
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creator Kwak, Young-Ho
Jung, Inhwa
Lee, Hyung-Dong
Choi, Young-Jung
Kumar, Yogendera
Kim, Chulwoo
description A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18mum CMOS process, the control block of the proposed driver occupies 0.009mm 2 and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.
doi_str_mv 10.1109/ISSCC.2007.373467
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Clocks
Crosstalk
Delay
Detectors
Driver circuits
Inverters
Open loop systems
Phase locked loops
Signal generators
Voltage control
title A One-Cycle Lock Time Slew-Rate-Controlled Output Driver
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