A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology
Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of...
Gespeichert in:
| Hauptverfasser: | , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 313 |
|---|---|
| container_issue | |
| container_start_page | 312 |
| container_title | |
| container_volume | |
| creator | Gebara, Fadi H. Schaub, Jeremy D. Nguyen, Tuyet Y. Pena, Jarom Vo, Ivan Boerstler, David Nowka, Kevin J. |
| description | Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology |
| doi_str_mv | 10.1109/ISSCC.2007.373419 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4242390</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4242390</ieee_id><sourcerecordid>4242390</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-4e72b0c77c812ddf3522263a0207bb1fdc7696c9e8930844e8c50e2dddf6c6003</originalsourceid><addsrcrecordid>eNo1j81Kw0AURsc_MK19AHEzL5B6Z-7MnZlliTUNFCokuC3JZKLRNJGkm_r0FtTVtziHAx9j9wKWQoB7zPI8SZYSwCzRoBLugi2csUJJpcBq1JcskmgotgR0xWb_QMI1i0A4jEkj3LLZNH0AgHZkI0YrLl65sOnmmyfd4D95Gvowlsdh5G3PS066P_CXpzjfZbwI_r0fuuHtdMdumrKbwuJv56x4XhfJJt7u0ixZbePWwTFWwcgKvDHeClnXDWopJWEJEkxViab2hhx5F6xDsEoF6zWEs1k35AkA5-zhN9uGEPZfY3sox9P-_EuiA_wBgYlGMQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Gebara, Fadi H. ; Schaub, Jeremy D. ; Nguyen, Tuyet Y. ; Pena, Jarom ; Vo, Ivan ; Boerstler, David ; Nowka, Kevin J.</creator><creatorcontrib>Gebara, Fadi H. ; Schaub, Jeremy D. ; Nguyen, Tuyet Y. ; Pena, Jarom ; Vo, Ivan ; Boerstler, David ; Nowka, Kevin J.</creatorcontrib><description>Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology</description><identifier>ISSN: 0193-6530</identifier><identifier>ISBN: 1424408520</identifier><identifier>ISBN: 9781424408528</identifier><identifier>EISSN: 2376-8606</identifier><identifier>EISBN: 9781424408535</identifier><identifier>EISBN: 1424408539</identifier><identifier>DOI: 10.1109/ISSCC.2007.373419</identifier><language>eng</language><publisher>IEEE</publisher><subject>Charge pumps ; Circuits ; Clocks ; Filters ; Frequency ; Inverters ; Jitter ; Phase locked loops ; Voltage ; Voltage-controlled oscillators</subject><ispartof>2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.312-313</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4242390$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4242390$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gebara, Fadi H.</creatorcontrib><creatorcontrib>Schaub, Jeremy D.</creatorcontrib><creatorcontrib>Nguyen, Tuyet Y.</creatorcontrib><creatorcontrib>Pena, Jarom</creatorcontrib><creatorcontrib>Vo, Ivan</creatorcontrib><creatorcontrib>Boerstler, David</creatorcontrib><creatorcontrib>Nowka, Kevin J.</creatorcontrib><title>A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology</title><title>2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers</title><addtitle>ISSCC</addtitle><description>Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology</description><subject>Charge pumps</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Filters</subject><subject>Frequency</subject><subject>Inverters</subject><subject>Jitter</subject><subject>Phase locked loops</subject><subject>Voltage</subject><subject>Voltage-controlled oscillators</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>1424408520</isbn><isbn>9781424408528</isbn><isbn>9781424408535</isbn><isbn>1424408539</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j81Kw0AURsc_MK19AHEzL5B6Z-7MnZlliTUNFCokuC3JZKLRNJGkm_r0FtTVtziHAx9j9wKWQoB7zPI8SZYSwCzRoBLugi2csUJJpcBq1JcskmgotgR0xWb_QMI1i0A4jEkj3LLZNH0AgHZkI0YrLl65sOnmmyfd4D95Gvowlsdh5G3PS066P_CXpzjfZbwI_r0fuuHtdMdumrKbwuJv56x4XhfJJt7u0ixZbePWwTFWwcgKvDHeClnXDWopJWEJEkxViab2hhx5F6xDsEoF6zWEs1k35AkA5-zhN9uGEPZfY3sox9P-_EuiA_wBgYlGMQ</recordid><startdate>200702</startdate><enddate>200702</enddate><creator>Gebara, Fadi H.</creator><creator>Schaub, Jeremy D.</creator><creator>Nguyen, Tuyet Y.</creator><creator>Pena, Jarom</creator><creator>Vo, Ivan</creator><creator>Boerstler, David</creator><creator>Nowka, Kevin J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200702</creationdate><title>A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology</title><author>Gebara, Fadi H. ; Schaub, Jeremy D. ; Nguyen, Tuyet Y. ; Pena, Jarom ; Vo, Ivan ; Boerstler, David ; Nowka, Kevin J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-4e72b0c77c812ddf3522263a0207bb1fdc7696c9e8930844e8c50e2dddf6c6003</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Charge pumps</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Filters</topic><topic>Frequency</topic><topic>Inverters</topic><topic>Jitter</topic><topic>Phase locked loops</topic><topic>Voltage</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Gebara, Fadi H.</creatorcontrib><creatorcontrib>Schaub, Jeremy D.</creatorcontrib><creatorcontrib>Nguyen, Tuyet Y.</creatorcontrib><creatorcontrib>Pena, Jarom</creatorcontrib><creatorcontrib>Vo, Ivan</creatorcontrib><creatorcontrib>Boerstler, David</creatorcontrib><creatorcontrib>Nowka, Kevin J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gebara, Fadi H.</au><au>Schaub, Jeremy D.</au><au>Nguyen, Tuyet Y.</au><au>Pena, Jarom</au><au>Vo, Ivan</au><au>Boerstler, David</au><au>Nowka, Kevin J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology</atitle><btitle>2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers</btitle><stitle>ISSCC</stitle><date>2007-02</date><risdate>2007</risdate><spage>312</spage><epage>313</epage><pages>312-313</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>1424408520</isbn><isbn>9781424408528</isbn><eisbn>9781424408535</eisbn><eisbn>1424408539</eisbn><abstract>Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2007.373419</doi><tpages>2</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0193-6530 |
| ispartof | 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.312-313 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_4242390 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Charge pumps Circuits Clocks Filters Frequency Inverters Jitter Phase locked loops Voltage Voltage-controlled oscillators |
| title | A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T22%3A40%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%201V%2018GHz%20Clock%20Generator%20in%20a%2065nm%20PD-SOI%20Technology&rft.btitle=2007%20IEEE%20International%20Solid-State%20Circuits%20Conference.%20Digest%20of%20Technical%20Papers&rft.au=Gebara,%20Fadi%20H.&rft.date=2007-02&rft.spage=312&rft.epage=313&rft.pages=312-313&rft.issn=0193-6530&rft.eissn=2376-8606&rft.isbn=1424408520&rft.isbn_list=9781424408528&rft_id=info:doi/10.1109/ISSCC.2007.373419&rft_dat=%3Cieee_6IE%3E4242390%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424408535&rft.eisbn_list=1424408539&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4242390&rfr_iscdi=true |