A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology

Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of...

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Bibliographische Detailangaben
Hauptverfasser:	Gebara, Fadi H., Schaub, Jeremy D., Nguyen, Tuyet Y., Pena, Jarom, Vo, Ivan, Boerstler, David, Nowka, Kevin J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Charge pumps Circuits Clocks Filters Frequency Inverters Jitter Phase locked loops Voltage Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:	Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2times lock range and a maximum frequency of 24.6GHz with 1.28ps rms jitter at 1V. The high-V, PLL exhibits a 3.5times lock range at 6% lower frequency. The 0.18mm 2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology
ISSN:	0193-6530 2376-8606
DOI:	10.1109/ISSCC.2007.373419