High-Throughput LDPC Decoders Using A Multiple Split-Row Method
We propose the "multi-split-row'" LDPC decoding method which allows further reductions in routing complexity, greater throughput, and smaller circuit area implementations compared to the previously proposed split-row decoding method. Multi-split-row is especially useful for regular hi...
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| creator | Mohsenin, T. Baas, B. M. |
| description | We propose the "multi-split-row'" LDPC decoding method which allows further reductions in routing complexity, greater throughput, and smaller circuit area implementations compared to the previously proposed split-row decoding method. Multi-split-row is especially useful for regular high row weight LDPC codes. A 2048-bit full parallel decoder is implemented in a 0.18 μm CMOS technology using standard MinSum, split-row-2 and split-row-4 methods. The split-row-4 decoder delivers 7.1 Gbps throughput with 15 decoding iterations, and has 3.2 times smaller circuit area and 5.2 times higher throughput than the standard MinSum decoder. |
| doi_str_mv | 10.1109/ICASSP.2007.366160 |
| format | Conference Proceeding |
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The split-row-4 decoder delivers 7.1 Gbps throughput with 15 decoding iterations, and has 3.2 times smaller circuit area and 5.2 times higher throughput than the standard MinSum decoder.</description><subject>CMOS technology</subject><subject>Digital signal processors</subject><subject>Digital video broadcasting</subject><subject>Equations</subject><subject>Hardware</subject><subject>Integrated circuit interconnections</subject><subject>Iterative algorithms</subject><subject>Iterative decoding</subject><subject>LDPC codes</subject><subject>Message passing</subject><subject>Parallel algorithms</subject><subject>Parallel architectures</subject><subject>Parity check codes</subject><subject>Throughput</subject><subject>Very-large-scale integration</subject><issn>1520-6149</issn><issn>2379-190X</issn><isbn>9781424407279</isbn><isbn>1424407273</isbn><isbn>9781424407286</isbn><isbn>1424407281</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVj8lKxEAYhNsNjOO8gF76BTr-vaSXkwwZdYQMDmYGvA1ZupOWaEIWxLc3oBfrUHX4oKhC6IZCSCmYu-d4laa7kAGokEtJJZygpVGaCiYEKKblKQoYV4ZQA29n_5gy5yigEQMiqTCX6GoY3gFAK6EDdL_xVU32dd9OVd1NI07WuxivbdGWth_wYfCfFV7h7dSMvmssTrvGj-S1_cJbO9ZteY0uXNYMdvmXC3R4fNjHG5K8PM2jE-KpikbiHBhlLM-Z4LmMipw7pR2dnRWFMNwwlmsVZbkr5xOgZVG6MjdCCxFpXkZ8gW5_e7219tj1_iPrv4-CUcVn_QCCoUz-</recordid><startdate>200704</startdate><enddate>200704</enddate><creator>Mohsenin, T.</creator><creator>Baas, B. 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M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mohsenin, T.</au><au>Baas, B. M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High-Throughput LDPC Decoders Using A Multiple Split-Row Method</atitle><btitle>2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07</btitle><stitle>ICASSP</stitle><date>2007-04</date><risdate>2007</risdate><volume>2</volume><spage>II-13</spage><epage>II-16</epage><pages>II-13-II-16</pages><issn>1520-6149</issn><eissn>2379-190X</eissn><isbn>9781424407279</isbn><isbn>1424407273</isbn><eisbn>9781424407286</eisbn><eisbn>1424407281</eisbn><abstract>We propose the "multi-split-row'" LDPC decoding method which allows further reductions in routing complexity, greater throughput, and smaller circuit area implementations compared to the previously proposed split-row decoding method. Multi-split-row is especially useful for regular high row weight LDPC codes. A 2048-bit full parallel decoder is implemented in a 0.18 μm CMOS technology using standard MinSum, split-row-2 and split-row-4 methods. The split-row-4 decoder delivers 7.1 Gbps throughput with 15 decoding iterations, and has 3.2 times smaller circuit area and 5.2 times higher throughput than the standard MinSum decoder.</abstract><pub>IEEE</pub><doi>10.1109/ICASSP.2007.366160</doi></addata></record> |
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| ispartof | 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07, 2007, Vol.2, p.II-13-II-16 |
| issn | 1520-6149 2379-190X |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS technology Digital signal processors Digital video broadcasting Equations Hardware Integrated circuit interconnections Iterative algorithms Iterative decoding LDPC codes Message passing Parallel algorithms Parallel architectures Parity check codes Throughput Very-large-scale integration |
| title | High-Throughput LDPC Decoders Using A Multiple Split-Row Method |
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