A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter

This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jong-Kwan Woo, Hyunjoong Lee, Woo-Yeol Shin, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Charge pumps Circuits Clocks CMOS technology Detectors Filters Frequency Jitter Phase locked loops
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!