A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment
As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced b...
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| creator | You-Gang Chen I-Chyn Wey An-Yeu Wu, A. |
| description | As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively. |
| doi_str_mv | 10.1109/ASSCC.2006.357909 |
| format | Conference Proceeding |
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In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.</description><subject>Circuit noise</subject><subject>Circuit synthesis</subject><subject>Crosstalk</subject><subject>Dynamic voltage scaling</subject><subject>Mirrors</subject><subject>MOS devices</subject><subject>Noise reduction</subject><subject>Signal to noise ratio</subject><subject>Threshold voltage</subject><subject>Working environment noise</subject><isbn>9780780397347</isbn><isbn>0780397347</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjFFLwzAUhQMiKHM_QHzJH-i8adKk93F0UwdjDjufR5rduMiaSro59u-t6OHA4TscDmP3AiZCAD5O67qqJjmAnsjCIOAVG6MpYbBEI5W5YeO-_4RBEnWBxS1zU76iM191oads0x0o2Xjks0u0bXC8CsmdwsDUh4_Iz-G45_O4t9HRjq9na76m5LvU_hb8FHeU-LI783r1Nsy-Q-piS_F4x669PfQ0_s8Re3-ab6qXbPn6vKimyywIKTHTsinBEqEENI4kaWdIaV-axhoQLle59UI06L0G1XhPeWn8zjXaAlpQcsQe_n4DEW2_UmhtumyVQKNVKX8AQOBUfA</recordid><startdate>200611</startdate><enddate>200611</enddate><creator>You-Gang Chen</creator><creator>I-Chyn Wey</creator><creator>An-Yeu Wu, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200611</creationdate><title>A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment</title><author>You-Gang Chen ; I-Chyn Wey ; An-Yeu Wu, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1339-63b80aee93097ce3e6c7e46f87ba701c242af11b9ff604bffe287fdcb6a09a043</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Circuit noise</topic><topic>Circuit synthesis</topic><topic>Crosstalk</topic><topic>Dynamic voltage scaling</topic><topic>Mirrors</topic><topic>MOS devices</topic><topic>Noise reduction</topic><topic>Signal to noise ratio</topic><topic>Threshold voltage</topic><topic>Working environment noise</topic><toplevel>online_resources</toplevel><creatorcontrib>You-Gang Chen</creatorcontrib><creatorcontrib>I-Chyn Wey</creatorcontrib><creatorcontrib>An-Yeu Wu, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>You-Gang Chen</au><au>I-Chyn Wey</au><au>An-Yeu Wu, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment</atitle><btitle>2006 IEEE Asian Solid-State Circuits Conference</btitle><stitle>ASSCC</stitle><date>2006-11</date><risdate>2006</risdate><spage>295</spage><epage>298</epage><pages>295-298</pages><isbn>9780780397347</isbn><isbn>0780397347</isbn><abstract>As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.</abstract><pub>IEEE</pub><doi>10.1109/ASSCC.2006.357909</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit noise Circuit synthesis Crosstalk Dynamic voltage scaling Mirrors MOS devices Noise reduction Signal to noise ratio Threshold voltage Working environment noise |
| title | A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment |
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