Fast Electrical Correction Using Resizing and Buffering

Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a circuit for optimization, the circuit has to be electrically clean - i.e., slews on each pin have to be within certain limi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Karandikar, S.K., Alpert, C.J., Yildiz, M.C., Villarrubia, P., Quay, S., Mahmud, T.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitance Circuits Delay Design optimization Electronic design automation and methodology Energy consumption Laboratories Optimization methods Silicon Timing
Online-Zugang:	Volltext bestellen
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