Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention
For retention improvement in scaled SONOS-type nonvolatile memory, deep traps with controllable density were formed by adding metal impurities into gate oxide. We find that Ti additives create deep traps in silicon dioxide, with high electron capture efficiency Charge storage node changed from TiO 2...
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| creator | Sunamura, H. Ikarashi, T. Morioka, A. Kotsuji, S. Oshida, M. Ikarashi, N. Fujieda, S. Watanabe, H. |
| description | For retention improvement in scaled SONOS-type nonvolatile memory, deep traps with controllable density were formed by adding metal impurities into gate oxide. We find that Ti additives create deep traps in silicon dioxide, with high electron capture efficiency Charge storage node changed from TiO 2 floating-gate (15Aring) to nano-crystals (3Aring), and further to atomic-sized traps (0.4Aring) by decreasing Ti amount. Discrete atomic-sized traps successfully suppressed lateral charge redistribution, improving retention at 150degC |
| doi_str_mv | 10.1109/IEDM.2006.346949 |
| format | Conference Proceeding |
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Discrete atomic-sized traps successfully suppressed lateral charge redistribution, improving retention at 150degC</description><subject>Additives</subject><subject>Dielectrics</subject><subject>Electron traps</subject><subject>Gold</subject><subject>Hafnium</subject><subject>Impurities</subject><subject>Nonvolatile memory</subject><subject>Silicon compounds</subject><subject>SONOS devices</subject><subject>Temperature</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>142440438X</isbn><isbn>9781424404384</isbn><isbn>9781424404391</isbn><isbn>1424404398</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kDtPwzAURs1Loi3dkVj8B1KuH4ntEZUClYoY6NCtcuKb1qh5yHGQ8u9pBEzfcI7O8BFyz2DBGJjH9er5fcEBsoWQmZHmgsyN0kxyKUEKwy7JhLM0S4Cp3RWZ_gO9uyYTYJlImGH6lky77guAq9SkEzJ89m0bsOt8U9OmpCcbMdgTLY42HJAGdL6Lwed9HIW-8_WBWvdt6wId9VXbBx8HGoNtaYVVEwZaNmEEofke3aM_HGnEqj1XYx_GYsR6jN2Rm9KeOpz_7YxsX1bb5Vuy-XhdL582iTcQkxRFIbljJkOnrc1dITOllTK5FdyiQLTOgZZO5Ci5LqBQJUcBZxl1CkLMyMNv1iPivg2-smHYS5aej5HiB0c0ZVA</recordid><startdate>200612</startdate><enddate>200612</enddate><creator>Sunamura, H.</creator><creator>Ikarashi, T.</creator><creator>Morioka, A.</creator><creator>Kotsuji, S.</creator><creator>Oshida, M.</creator><creator>Ikarashi, N.</creator><creator>Fujieda, S.</creator><creator>Watanabe, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200612</creationdate><title>Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention</title><author>Sunamura, H. ; Ikarashi, T. ; Morioka, A. ; Kotsuji, S. ; Oshida, M. ; Ikarashi, N. ; Fujieda, S. ; Watanabe, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-5e3c42d196ed8aabdc4678779ba32ae3eeadd084d3be428c0c7f2e30d8ae85033</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Additives</topic><topic>Dielectrics</topic><topic>Electron traps</topic><topic>Gold</topic><topic>Hafnium</topic><topic>Impurities</topic><topic>Nonvolatile memory</topic><topic>Silicon compounds</topic><topic>SONOS devices</topic><topic>Temperature</topic><toplevel>online_resources</toplevel><creatorcontrib>Sunamura, H.</creatorcontrib><creatorcontrib>Ikarashi, T.</creatorcontrib><creatorcontrib>Morioka, A.</creatorcontrib><creatorcontrib>Kotsuji, S.</creatorcontrib><creatorcontrib>Oshida, M.</creatorcontrib><creatorcontrib>Ikarashi, N.</creatorcontrib><creatorcontrib>Fujieda, S.</creatorcontrib><creatorcontrib>Watanabe, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sunamura, H.</au><au>Ikarashi, T.</au><au>Morioka, A.</au><au>Kotsuji, S.</au><au>Oshida, M.</au><au>Ikarashi, N.</au><au>Fujieda, S.</au><au>Watanabe, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention</atitle><btitle>2006 International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2006-12</date><risdate>2006</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>142440438X</isbn><isbn>9781424404384</isbn><eisbn>9781424404391</eisbn><eisbn>1424404398</eisbn><abstract>For retention improvement in scaled SONOS-type nonvolatile memory, deep traps with controllable density were formed by adding metal impurities into gate oxide. We find that Ti additives create deep traps in silicon dioxide, with high electron capture efficiency Charge storage node changed from TiO 2 floating-gate (15Aring) to nano-crystals (3Aring), and further to atomic-sized traps (0.4Aring) by decreasing Ti amount. Discrete atomic-sized traps successfully suppressed lateral charge redistribution, improving retention at 150degC</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2006.346949</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0163-1918 |
| ispartof | 2006 International Electron Devices Meeting, 2006, p.1-4 |
| issn | 0163-1918 2156-017X |
| language | eng |
| recordid | cdi_ieee_primary_4154384 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Additives Dielectrics Electron traps Gold Hafnium Impurities Nonvolatile memory Silicon compounds SONOS devices Temperature |
| title | Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention |
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