A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL
We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and...
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| creator | Nii, H. Sanuki, T. Okayama, Y. Ota, K. Iwamoto, T. Fujimaki, T. Kimura, T. Watanabe, R. Komoda, T. Eiho, A. Aikawa, K. Yamaguchi, H. Morimoto, R. Ohshima, K. Yokoyama, T. Matsumoto, T. Hachimine, K. Sogo, Y. Shino, S. Kanai, S. Yamazak, T. Takahashi, S. Maeda, H. Iwata, T. Ohno, K. Takegawa, Y. Oishi, A. Togo, M. Fukasaku, K. Takasu, Y. Yamasaki, H. Inokuma, H. Matsuo, K. Sato, T. Nakazawa, M. Katagiri, T. Nakazawa, K. Shinyama, T. Tetsuka, T. Fujita, S. Kagawa, Y. Nagaoka, K. Muramatsu, S. Iwasa, S. Mimotogi, S. Yoshida, K. Sunouchi, K. Iwai, M. Saito, M. Ikeda, M. Enomoto, Y. Naruse, H. Imai, K. Yamada, S. Nagashima, N. Kuwata, T. Matsuoka, F. |
| description | We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7) |
| doi_str_mv | 10.1109/IEDM.2006.346878 |
| format | Conference Proceeding |
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Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)</description><subject>Boron</subject><subject>CMOS technology</subject><subject>Degradation</subject><subject>DSL</subject><subject>Large scale integration</subject><subject>Lithography</subject><subject>Logic</subject><subject>MOSFET circuits</subject><subject>Random access memory</subject><subject>Surface-mount technology</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>142440438X</isbn><isbn>9781424404384</isbn><isbn>9781424404391</isbn><isbn>1424404398</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1jktPwkAYRcdXIqh7EzffUhfFmc57iYBCUoQETNiRcToto32QaRvDT_JfqlFX9-ae5OQidE3wgBCs72eT8XwQYywGlAkl1RG60lIRFjOGGdXkGPViwkWEidycoP4_UJtT1MNE0Ihoos5Rv2neMI4l17yHPofAeFXC1Oc7WLqQ1aE0lXXw0BXvkNS5t7AsTPuzw9rZXVUXdX6A29F8sRJ30DW-yuGlaIP5dTwPb8kAyzuYlaULja8rSHy7q_Ng9rsDfHx3mB5eg09h3JkiGpvSNNZVDlZt6GzbBQemSmFZh7prvh98RO_wMFkkl-gsM0Xjrv7yAq0fJ-vRNEoWT7PRMIm8xm0kpU1T7nSMGaMZe1XYWqM5toYbGTtBRIYVUyqjkrhUcCp4zGWmnFApThWlF-jmV-udc9t98KUJhy0jnMVa0i8qPm9N</recordid><startdate>200612</startdate><enddate>200612</enddate><creator>Nii, H.</creator><creator>Sanuki, T.</creator><creator>Okayama, Y.</creator><creator>Ota, K.</creator><creator>Iwamoto, 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T. ; Kimura, T. ; Watanabe, R. ; Komoda, T. ; Eiho, A. ; Aikawa, K. ; Yamaguchi, H. ; Morimoto, R. ; Ohshima, K. ; Yokoyama, T. ; Matsumoto, T. ; Hachimine, K. ; Sogo, Y. ; Shino, S. ; Kanai, S. ; Yamazak, T. ; Takahashi, S. ; Maeda, H. ; Iwata, T. ; Ohno, K. ; Takegawa, Y. ; Oishi, A. ; Togo, M. ; Fukasaku, K. ; Takasu, Y. ; Yamasaki, H. ; Inokuma, H. ; Matsuo, K. ; Sato, T. ; Nakazawa, M. ; Katagiri, T. ; Nakazawa, K. ; Shinyama, T. ; Tetsuka, T. ; Fujita, S. ; Kagawa, Y. ; Nagaoka, K. ; Muramatsu, S. ; Iwasa, S. ; Mimotogi, S. ; Yoshida, K. ; Sunouchi, K. ; Iwai, M. ; Saito, M. ; Ikeda, M. ; Enomoto, Y. ; Naruse, H. ; Imai, K. ; Yamada, S. ; Nagashima, N. ; Kuwata, T. ; Matsuoka, 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S.</creatorcontrib><creatorcontrib>Nagashima, N.</creatorcontrib><creatorcontrib>Kuwata, T.</creatorcontrib><creatorcontrib>Matsuoka, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nii, H.</au><au>Sanuki, T.</au><au>Okayama, Y.</au><au>Ota, K.</au><au>Iwamoto, T.</au><au>Fujimaki, T.</au><au>Kimura, T.</au><au>Watanabe, R.</au><au>Komoda, T.</au><au>Eiho, A.</au><au>Aikawa, K.</au><au>Yamaguchi, H.</au><au>Morimoto, R.</au><au>Ohshima, K.</au><au>Yokoyama, T.</au><au>Matsumoto, T.</au><au>Hachimine, K.</au><au>Sogo, Y.</au><au>Shino, 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BEOL</atitle><btitle>2006 International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2006-12</date><risdate>2006</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>142440438X</isbn><isbn>9781424404384</isbn><eisbn>9781424404391</eisbn><eisbn>1424404398</eisbn><abstract>We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2006.346878</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0163-1918 |
| ispartof | 2006 International Electron Devices Meeting, 2006, p.1-4 |
| issn | 0163-1918 2156-017X |
| language | eng |
| recordid | cdi_ieee_primary_4154297 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Boron CMOS technology Degradation DSL Large scale integration Lithography Logic MOSFET circuits Random access memory Surface-mount technology |
| title | A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T12%3A33%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%2045nm%20High%20Performance%20Bulk%20Logic%20Platform%20Technology%20(CMOS6)%20using%20Ultra%20High%20NA(1.07)%20Immersion%20Lithography%20with%20Hybrid%20Dual-Damascene%20Structure%20and%20Porous%20Low-k%20BEOL&rft.btitle=2006%20International%20Electron%20Devices%20Meeting&rft.au=Nii,%20H.&rft.date=2006-12&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.issn=0163-1918&rft.eissn=2156-017X&rft.isbn=142440438X&rft.isbn_list=9781424404384&rft_id=info:doi/10.1109/IEDM.2006.346878&rft_dat=%3Cieee_6IE%3E4154297%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424404391&rft.eisbn_list=1424404398&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4154297&rfr_iscdi=true |