A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance est...

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Hauptverfasser:	Sankaran, S., Arai, S., Augur, R., Beck, M., Biery, G., Bolom, T., Bonilla, G., Bravo, O., Chanda, K., Chae, M., Chen, F., Clevenger, L., Cohen, S., Cowley, A., Davis, P., Demarest, J., Doyle, J., Dimitrakopoulos, C., Economikos, L., Edelstein, D., Farooq, M., Filippi, R., Fitzsimmons, J., Fuller, N., Gates, S.M., Greco, S.E., Grill, A., Grunow, S., Hannon, R., Ida, K., Jung, D., Kaltalioglu, E., Kelling, M., Ko, T., Kumar, K., Labelle, C., Landis, H., Lane, M.W., Landers, W., Lee, M., Li, W., Liniger, E., Liu, X., Lloyd, J.R., Liu, W., Lustig, N., Malone, K., Marokkey, S., Matusiewicz, G., McLaughlin, P.S., McLaughlin, P.V., Mehta, S., Melville, I., Miyata, K., Moon, B., Nitta, S., Nguyen, D., Nicholson, L., Nielsen, D., Ong, P., Patel, K., Patel, V., Park, W., Pellerin, J., Ponoth, S., Petrarca, K., Rath, D., Restaino, D., Rhee, S., Ryan, E.T., Shoba, H., Simon, A., Simonyi, E., Shaw, T.M., Spooner, T., Standaert, T., Sucharitaves, J., Tian, C., Wendt, H., Werking, J., Widodo, J., Wiggins, L., Wisnieff, R., Ivers, T.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit optimization CMOS technology Costs Etching Integrated circuit reliability Mechanical factors Packaging System performance Wire Wiring
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