PAD: A Design Space Exploration Model For Reconfigurable Systems
Designing an optimized architecture for reconfigurable computing is a very complicated task due to its vast design space. In this paper, we present a novel design exploration model - PAD (power, area and delay). Based on this model, total cost and average cost of application are computed and reconfi...
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| creator | Kang Sun Xuezeng Pan Jimin Wang Lingdi Ping |
| description | Designing an optimized architecture for reconfigurable computing is a very complicated task due to its vast design space. In this paper, we present a novel design exploration model - PAD (power, area and delay). Based on this model, total cost and average cost of application are computed and reconfigurable architecture design space is explored with average cost. This method can effectively help the designer to create appropriate reconfigurable architecture for an application domain at the beginning of design |
| doi_str_mv | 10.1109/ITNG.2007.146 |
| format | Conference Proceeding |
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In this paper, we present a novel design exploration model - PAD (power, area and delay). Based on this model, total cost and average cost of application are computed and reconfigurable architecture design space is explored with average cost. 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In this paper, we present a novel design exploration model - PAD (power, area and delay). Based on this model, total cost and average cost of application are computed and reconfigurable architecture design space is explored with average cost. This method can effectively help the designer to create appropriate reconfigurable architecture for an application domain at the beginning of design</description><subject>Atherosclerosis</subject><subject>Capacitance</subject><subject>Computer architecture</subject><subject>Costs</subject><subject>Delay</subject><subject>Design methodology</subject><subject>Reconfigurable architectures</subject><subject>Semiconductor device modeling</subject><subject>Space exploration</subject><subject>Space technology</subject><isbn>9780769527765</isbn><isbn>0769527760</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzMtKw0AUgOEBEZSapSs38wKJc-Y-rgy9WagXbF2XyfRMGUmTkKlg315B_823-wm5BVYBMHe_2r4sK86YqUDqC1I4Y5nRTnFjtLoiRc6f7DfhpFP6mjy-1bMHWtMZ5nTo6GbwAen8e2j70Z9S39Hnfo8tXfQjfcfQdzEdvkbftEg353zCY74hl9G3GYt_J-RjMd9On8r163I1rddlAqNOJXBnuRXcR-YbJ7l02gOzYEO0IF1wRqDSWjV7EaRjMUgRnVVKoTXAtBYTcvf3TYi4G8Z09ON5J0GB5VL8AIr7RPs</recordid><startdate>200704</startdate><enddate>200704</enddate><creator>Kang Sun</creator><creator>Xuezeng Pan</creator><creator>Jimin Wang</creator><creator>Lingdi Ping</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200704</creationdate><title>PAD: A Design Space Exploration Model For Reconfigurable Systems</title><author>Kang Sun ; Xuezeng Pan ; Jimin Wang ; Lingdi Ping</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-12982832af0ab942496a10818cf8149c973e5665bd3c490fc43f98555e8710663</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Atherosclerosis</topic><topic>Capacitance</topic><topic>Computer architecture</topic><topic>Costs</topic><topic>Delay</topic><topic>Design methodology</topic><topic>Reconfigurable architectures</topic><topic>Semiconductor device modeling</topic><topic>Space exploration</topic><topic>Space technology</topic><toplevel>online_resources</toplevel><creatorcontrib>Kang Sun</creatorcontrib><creatorcontrib>Xuezeng Pan</creatorcontrib><creatorcontrib>Jimin Wang</creatorcontrib><creatorcontrib>Lingdi Ping</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kang Sun</au><au>Xuezeng Pan</au><au>Jimin Wang</au><au>Lingdi Ping</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>PAD: A Design Space Exploration Model For Reconfigurable Systems</atitle><btitle>Fourth International Conference on Information Technology (ITNG'07)</btitle><stitle>ITNG</stitle><date>2007-04</date><risdate>2007</risdate><spage>964</spage><epage>965</epage><pages>964-965</pages><isbn>9780769527765</isbn><isbn>0769527760</isbn><abstract>Designing an optimized architecture for reconfigurable computing is a very complicated task due to its vast design space. In this paper, we present a novel design exploration model - PAD (power, area and delay). Based on this model, total cost and average cost of application are computed and reconfigurable architecture design space is explored with average cost. This method can effectively help the designer to create appropriate reconfigurable architecture for an application domain at the beginning of design</abstract><pub>IEEE</pub><doi>10.1109/ITNG.2007.146</doi><tpages>2</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Atherosclerosis Capacitance Computer architecture Costs Delay Design methodology Reconfigurable architectures Semiconductor device modeling Space exploration Space technology |
| title | PAD: A Design Space Exploration Model For Reconfigurable Systems |
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