Ball impact responses and failure analysis of wafer-level chip-scale packages
The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test...
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creator | Yi-Shao Lai Chang-Lin Yeh Hsiao-Chuan Chang Chin-Li Kao |
description | The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, we present BIT results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after BIT, respectively. The explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles were presented. |
doi_str_mv | 10.1109/EPTC.2006.342712 |
format | Conference Proceeding |
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The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, we present BIT results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after BIT, respectively. The explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles were presented.</description><identifier>ISBN: 9781424406647</identifier><identifier>ISBN: 1424406641</identifier><identifier>EISBN: 9781424406654</identifier><identifier>EISBN: 142440665X</identifier><identifier>DOI: 10.1109/EPTC.2006.342712</identifier><language>eng</language><subject>Chip scale packaging ; Failure analysis ; Force measurement ; Intermetallic ; Lead ; Semiconductor device measurement ; Shearing ; Soldering ; Testing ; Wafer scale integration</subject><ispartof>2006 8th Electronics Packaging Technology Conference, 2006, p.179-184</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4147241$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2057,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4147241$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yi-Shao Lai</creatorcontrib><creatorcontrib>Chang-Lin Yeh</creatorcontrib><creatorcontrib>Hsiao-Chuan Chang</creatorcontrib><creatorcontrib>Chin-Li Kao</creatorcontrib><title>Ball impact responses and failure analysis of wafer-level chip-scale packages</title><title>2006 8th Electronics Packaging Technology Conference</title><addtitle>EPTC</addtitle><description>The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, we present BIT results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after BIT, respectively. The explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles were presented.</description><subject>Chip scale packaging</subject><subject>Failure analysis</subject><subject>Force measurement</subject><subject>Intermetallic</subject><subject>Lead</subject><subject>Semiconductor device measurement</subject><subject>Shearing</subject><subject>Soldering</subject><subject>Testing</subject><subject>Wafer scale integration</subject><isbn>9781424406647</isbn><isbn>1424406641</isbn><isbn>9781424406654</isbn><isbn>142440665X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVjEFLw0AUhFdEUGrugpf9A4nvbV425qihWqGih3oub5O3urptQ7Yq_fcG9OJc5huYGaUuEApEaK7mz6u2MAC2KMnUaI5U1tTXSIYIrK3o-F-m-lRlKb3DpLIha_FMPd5yjDpsBu72epQ07LZJkuZtrz2H-DnKxBwPKSS98_qbvYx5lC-JunsLQ546jqKn9Qe_SjpXJ55jkuzPZ-rlbr5qF_ny6f6hvVnmAetqn5NnFu89GSld7yqDlZcG0TvH1IMFJ3YC21ns-9JP1Q4sgwPvDANjOVOXv79BRNbDGDY8HtaEVBvC8gdLIVGP</recordid><startdate>200612</startdate><enddate>200612</enddate><creator>Yi-Shao Lai</creator><creator>Chang-Lin Yeh</creator><creator>Hsiao-Chuan Chang</creator><creator>Chin-Li Kao</creator><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200612</creationdate><title>Ball impact responses and failure analysis of wafer-level chip-scale packages</title><author>Yi-Shao Lai ; Chang-Lin Yeh ; Hsiao-Chuan Chang ; Chin-Li Kao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-4faaefff42e3bdb5215fe911fbba4d060be6a4d6c61dd3feffc06a0b0fb2a0a13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Chip scale packaging</topic><topic>Failure analysis</topic><topic>Force measurement</topic><topic>Intermetallic</topic><topic>Lead</topic><topic>Semiconductor device measurement</topic><topic>Shearing</topic><topic>Soldering</topic><topic>Testing</topic><topic>Wafer scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Yi-Shao Lai</creatorcontrib><creatorcontrib>Chang-Lin Yeh</creatorcontrib><creatorcontrib>Hsiao-Chuan Chang</creatorcontrib><creatorcontrib>Chin-Li Kao</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yi-Shao Lai</au><au>Chang-Lin Yeh</au><au>Hsiao-Chuan Chang</au><au>Chin-Li Kao</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Ball impact responses and failure analysis of wafer-level chip-scale packages</atitle><btitle>2006 8th Electronics Packaging Technology Conference</btitle><stitle>EPTC</stitle><date>2006-12</date><risdate>2006</risdate><spage>179</spage><epage>184</epage><pages>179-184</pages><isbn>9781424406647</isbn><isbn>1424406641</isbn><eisbn>9781424406654</eisbn><eisbn>142440665X</eisbn><abstract>The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, we present BIT results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after BIT, respectively. The explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles were presented.</abstract><doi>10.1109/EPTC.2006.342712</doi><tpages>6</tpages></addata></record> |
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subjects | Chip scale packaging Failure analysis Force measurement Intermetallic Lead Semiconductor device measurement Shearing Soldering Testing Wafer scale integration |
title | Ball impact responses and failure analysis of wafer-level chip-scale packages |
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