Efficient Implementation of AES IP
The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estima...
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| creator | Yu-Jung Huang Yang-Shih Lin Kuang-Yu Hung Kuo-Chen Lin |
| description | The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estimation in FPGA implementation with Altera and Xilinx platforms are also presented. The hardware implementation results of the proposed architecture with Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation has less area cost as compared with previous relevant architecture. Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance |
| doi_str_mv | 10.1109/APCCAS.2006.342467 |
| format | Conference Proceeding |
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For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estimation in FPGA implementation with Altera and Xilinx platforms are also presented. The hardware implementation results of the proposed architecture with Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation has less area cost as compared with previous relevant architecture. Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance</description><identifier>ISBN: 9781424403868</identifier><identifier>ISBN: 9781424403875</identifier><identifier>ISBN: 1424403871</identifier><identifier>ISBN: 1424403863</identifier><identifier>DOI: 10.1109/APCCAS.2006.342467</identifier><language>eng</language><publisher>IEEE</publisher><subject>Advanced encryption standard ; Application specific integrated circuits ; Bandwidth ; Cell-Based library ; Cryptography ; Delay ; Field programmable gate arrays ; FPGA ; Galois Field ; Galois fields ; Hardware ; Libraries ; Mixcolumn ; NIST ; Power engineering and energy</subject><ispartof>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006, p.1418-1421</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4145667$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4145667$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yu-Jung Huang</creatorcontrib><creatorcontrib>Yang-Shih Lin</creatorcontrib><creatorcontrib>Kuang-Yu Hung</creatorcontrib><creatorcontrib>Kuo-Chen Lin</creatorcontrib><title>Efficient Implementation of AES IP</title><title>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems</title><addtitle>APCCAS</addtitle><description>The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. 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Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance</description><subject>Advanced encryption standard</subject><subject>Application specific integrated circuits</subject><subject>Bandwidth</subject><subject>Cell-Based library</subject><subject>Cryptography</subject><subject>Delay</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Galois Field</subject><subject>Galois fields</subject><subject>Hardware</subject><subject>Libraries</subject><subject>Mixcolumn</subject><subject>NIST</subject><subject>Power engineering and energy</subject><isbn>9781424403868</isbn><isbn>9781424403875</isbn><isbn>1424403871</isbn><isbn>1424403863</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjM1Kw0AURgdEUGpeQDfBfeLcuXfuTJYhRA0ULFTXZTI_MNK0pcnGtzegZ_Md-OAI8QiyBpDNS7vrunZfKym5RlLE5kYUjbGwOkm0bO9EMc_fcgUbNMT34rlPKfscT0s5TJdjnFZzSz6fynMq235fDrsHcZvccY7F_27E12v_2b1X24-3oWu3VQajl8qSJbBSe-0NIpsRRyJvkw8E7CCMFKIElSCY9ZBRKSYETlaTDq5RuBFPf90cYzxcrnly158DAWlmg7-5Ezu-</recordid><startdate>200612</startdate><enddate>200612</enddate><creator>Yu-Jung Huang</creator><creator>Yang-Shih Lin</creator><creator>Kuang-Yu Hung</creator><creator>Kuo-Chen Lin</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200612</creationdate><title>Efficient Implementation of AES IP</title><author>Yu-Jung Huang ; Yang-Shih Lin ; Kuang-Yu Hung ; Kuo-Chen Lin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-84841805c5c73367b3b44c8fcd416a1db4de012f1d7b440e2264316f8545da923</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Advanced encryption standard</topic><topic>Application specific integrated circuits</topic><topic>Bandwidth</topic><topic>Cell-Based library</topic><topic>Cryptography</topic><topic>Delay</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Galois Field</topic><topic>Galois fields</topic><topic>Hardware</topic><topic>Libraries</topic><topic>Mixcolumn</topic><topic>NIST</topic><topic>Power engineering and energy</topic><toplevel>online_resources</toplevel><creatorcontrib>Yu-Jung Huang</creatorcontrib><creatorcontrib>Yang-Shih Lin</creatorcontrib><creatorcontrib>Kuang-Yu Hung</creatorcontrib><creatorcontrib>Kuo-Chen Lin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yu-Jung Huang</au><au>Yang-Shih Lin</au><au>Kuang-Yu Hung</au><au>Kuo-Chen Lin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Efficient Implementation of AES IP</atitle><btitle>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems</btitle><stitle>APCCAS</stitle><date>2006-12</date><risdate>2006</risdate><spage>1418</spage><epage>1421</epage><pages>1418-1421</pages><isbn>9781424403868</isbn><isbn>9781424403875</isbn><isbn>1424403871</isbn><isbn>1424403863</isbn><abstract>The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estimation in FPGA implementation with Altera and Xilinx platforms are also presented. The hardware implementation results of the proposed architecture with Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation has less area cost as compared with previous relevant architecture. Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2006.342467</doi><tpages>4</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Advanced encryption standard Application specific integrated circuits Bandwidth Cell-Based library Cryptography Delay Field programmable gate arrays FPGA Galois Field Galois fields Hardware Libraries Mixcolumn NIST Power engineering and energy |
| title | Efficient Implementation of AES IP |
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