A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems
This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with...
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| creator | Young-Jae Cho Kyung-Hoon Lee Hee-Cheol Choi Young-Ju Kim Kyoung-Jun Moon Seung-Hoon Lee Seok-Bong Hyun Seong-Su Park |
| description | This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18mum 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral nonlinearities of the prototype ADC are within 1.00LSB and 1.25LSB, respectively. The dual-channel ADC has an active area of 4.0mm 2 and consumes 594mW at 1GS/s and 1.8V |
| doi_str_mv | 10.1109/APCCAS.2006.342420 |
| format | Conference Proceeding |
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| identifier | ISBN: 9781424403868 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | ADC Broadband amplifiers Circuit noise CMOS CMOS digital integrated circuits CMOS technology Differential amplifiers flash kickback Latches Noise reduction Power amplifiers Preamplifiers ultra wide band Ultra wideband technology |
| title | A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems |
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