A 1.2 billion operations per second video signal processing chip

Presents a new VLSI processor for image compression and machine vision which combines principles of multi-pipeline and array processing. The device is designed to function as a 2D vector accelerator, as is required for many image coding/processing/vision tasks. The device (DIP chip) is not specific...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yates, R., Evans, S., Ivey, P.A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Convolution Electronics packaging Image coding Image communication Kernel Read-write memory Reduced instruction set computing Signal processing algorithms Video signal processing
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