Delay/Phase Regeneration Circuits
Designs which require a phase relationship between two signals to be maintained along a link benefit from the use of repeaters which actively regenerate this relationship. This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues enco...
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| creator | D'Alessandro, C. Mokhov, A. Bystrov, A. Yakovlev, A. |
| description | Designs which require a phase relationship between two signals to be maintained along a link benefit from the use of repeaters which actively regenerate this relationship. This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues encountered in the design of such circuitry. The paper proposes various design solutions for the dual-rail case, extending the work to the multiple-rail case. A novel device which is able to reconstruct a sequence of events is also presented, the transition sequence encoder. Simulation results are provided with discussion on the relative performance. |
| doi_str_mv | 10.1109/ASYNC.2007.14 |
| format | Conference Proceeding |
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This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues encountered in the design of such circuitry. The paper proposes various design solutions for the dual-rail case, extending the work to the multiple-rail case. A novel device which is able to reconstruct a sequence of events is also presented, the transition sequence encoder. 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Simulation results are provided with discussion on the relative performance.</description><subject>Circuit simulation</subject><subject>Delay effects</subject><subject>Encoding</subject><subject>Integrated circuit interconnections</subject><subject>Maintenance</subject><subject>Microelectronics</subject><subject>Pipeline processing</subject><subject>Protocols</subject><subject>Repeaters</subject><subject>Signal design</subject><issn>1522-8681</issn><isbn>076952771X</isbn><isbn>9780769527710</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzE1Lw0AQgOEFFay1R09e6g9IOrMfM7vHEq0WShU_QE9lk0x0pVbJxkP_vYK-l-f2KnWGUCJCmM0fXtZVqQG4RHugToApOM2Mz4dqhE7rwpPHYzXJ-R1-M8Fw4JG6uJRt3M_u3mKW6b28yk76OKTP3bRKffOdhnyqjrq4zTL5d6yeFleP1U2xur1eVvNVkZDdUPjgfIdkHTWmxigdNB7REbbcCohHS9B2LbWoa9IWtPcca80SPAM1ZMbq_O-bRGTz1aeP2O83Fg2DYfMDNYY8gw</recordid><startdate>200703</startdate><enddate>200703</enddate><creator>D'Alessandro, C.</creator><creator>Mokhov, A.</creator><creator>Bystrov, A.</creator><creator>Yakovlev, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200703</creationdate><title>Delay/Phase Regeneration Circuits</title><author>D'Alessandro, C. ; Mokhov, A. ; Bystrov, A. ; Yakovlev, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-8958f16456c3b1aef0c811561d7de0e81460dfd6d12b62402887ab27e98706c63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Circuit simulation</topic><topic>Delay effects</topic><topic>Encoding</topic><topic>Integrated circuit interconnections</topic><topic>Maintenance</topic><topic>Microelectronics</topic><topic>Pipeline processing</topic><topic>Protocols</topic><topic>Repeaters</topic><topic>Signal design</topic><toplevel>online_resources</toplevel><creatorcontrib>D'Alessandro, C.</creatorcontrib><creatorcontrib>Mokhov, A.</creatorcontrib><creatorcontrib>Bystrov, A.</creatorcontrib><creatorcontrib>Yakovlev, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>D'Alessandro, C.</au><au>Mokhov, A.</au><au>Bystrov, A.</au><au>Yakovlev, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Delay/Phase Regeneration Circuits</atitle><btitle>13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)</btitle><stitle>ASYNC</stitle><date>2007-03</date><risdate>2007</risdate><spage>105</spage><epage>116</epage><pages>105-116</pages><issn>1522-8681</issn><isbn>076952771X</isbn><isbn>9780769527710</isbn><abstract>Designs which require a phase relationship between two signals to be maintained along a link benefit from the use of repeaters which actively regenerate this relationship. This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues encountered in the design of such circuitry. The paper proposes various design solutions for the dual-rail case, extending the work to the multiple-rail case. A novel device which is able to reconstruct a sequence of events is also presented, the transition sequence encoder. Simulation results are provided with discussion on the relative performance.</abstract><pub>IEEE</pub><doi>10.1109/ASYNC.2007.14</doi><tpages>12</tpages></addata></record> |
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| identifier | ISSN: 1522-8681 |
| ispartof | 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007, p.105-116 |
| issn | 1522-8681 |
| language | eng |
| recordid | cdi_ieee_primary_4137037 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation Delay effects Encoding Integrated circuit interconnections Maintenance Microelectronics Pipeline processing Protocols Repeaters Signal design |
| title | Delay/Phase Regeneration Circuits |
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