High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and en...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Dobkin, R., Perelman, Y., Liran, T., Ginosar, R., Kolodny, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Costs Delay Driver circuits Integrated circuit interconnections Power system interconnection Shift registers System-on-a-chip Throughput Transmitters
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