High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and en...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Dobkin, R., Perelman, Y., Liran, T., Ginosar, R., Kolodny, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Costs Delay Driver circuits Integrated circuit interconnections Power system interconnection Shift registers System-on-a-chip Throughput Transmitters
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page	14
container_issue
container_start_page	3
container_title
container_volume
creator	Dobkin, R. Perelman, Y. Liran, T. Ginosar, R. Kolodny, A.
description	A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.
doi_str_mv	10.1109/ASYNC.2007.20
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4137028</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4137028</ieee_id><sourcerecordid>4137028</sourcerecordid><originalsourceid>FETCH-LOGICAL-i280t-39a69ab7f26dd2f753743e2b25456ba512d59be642c16278c16846073742f76e3</originalsourceid><addsrcrecordid>eNotjL1OwzAURi0BEqV0ZGLxC7jY17GvPaaBUqSISvwImConcYghpFEckPr2RIJvON9ydAi5EHwpBLdX6ePbfbYEznHCETnjqK0CRPF6TGZCATCjjTglixg_-DRpJVqckdUmvDf0wY2evrgfz_rQ-zZ0vqJpPHRlM-y7_Xek246VTejpKows-iG4ll670dE8dJ_n5KR2bfSL_5-T5_XNU7Zh-fb2LktzFsDwkUnrtHUF1qCrCmpUEhPpoQCVKF04JaBStvA6gVJoQDPRJJrjpE229nJOLv-6wXu_64fw5YbDLhESORj5Cx9iR6I</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Dobkin, R. ; Perelman, Y. ; Liran, T. ; Ginosar, R. ; Kolodny, A.</creator><creatorcontrib>Dobkin, R. ; Perelman, Y. ; Liran, T. ; Ginosar, R. ; Kolodny, A.</creatorcontrib><description>A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.</description><identifier>ISSN: 1522-8681</identifier><identifier>ISBN: 076952771X</identifier><identifier>ISBN: 9780769527710</identifier><identifier>DOI: 10.1109/ASYNC.2007.20</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Costs ; Delay ; Driver circuits ; Integrated circuit interconnections ; Power system interconnection ; Shift registers ; System-on-a-chip ; Throughput ; Transmitters</subject><ispartof>13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007, p.3-14</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4137028$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4137028$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Dobkin, R.</creatorcontrib><creatorcontrib>Perelman, Y.</creatorcontrib><creatorcontrib>Liran, T.</creatorcontrib><creatorcontrib>Ginosar, R.</creatorcontrib><creatorcontrib>Kolodny, A.</creatorcontrib><title>High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link</title><title>13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)</title><addtitle>ASYNC</addtitle><description>A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.</description><subject>Clocks</subject><subject>Costs</subject><subject>Delay</subject><subject>Driver circuits</subject><subject>Integrated circuit interconnections</subject><subject>Power system interconnection</subject><subject>Shift registers</subject><subject>System-on-a-chip</subject><subject>Throughput</subject><subject>Transmitters</subject><issn>1522-8681</issn><isbn>076952771X</isbn><isbn>9780769527710</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjL1OwzAURi0BEqV0ZGLxC7jY17GvPaaBUqSISvwImConcYghpFEckPr2RIJvON9ydAi5EHwpBLdX6ePbfbYEznHCETnjqK0CRPF6TGZCATCjjTglixg_-DRpJVqckdUmvDf0wY2evrgfz_rQ-zZ0vqJpPHRlM-y7_Xek246VTejpKows-iG4ll670dE8dJ_n5KR2bfSL_5-T5_XNU7Zh-fb2LktzFsDwkUnrtHUF1qCrCmpUEhPpoQCVKF04JaBStvA6gVJoQDPRJJrjpE229nJOLv-6wXu_64fw5YbDLhESORj5Cx9iR6I</recordid><startdate>200703</startdate><enddate>200703</enddate><creator>Dobkin, R.</creator><creator>Perelman, Y.</creator><creator>Liran, T.</creator><creator>Ginosar, R.</creator><creator>Kolodny, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200703</creationdate><title>High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link</title><author>Dobkin, R. ; Perelman, Y. ; Liran, T. ; Ginosar, R. ; Kolodny, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i280t-39a69ab7f26dd2f753743e2b25456ba512d59be642c16278c16846073742f76e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Clocks</topic><topic>Costs</topic><topic>Delay</topic><topic>Driver circuits</topic><topic>Integrated circuit interconnections</topic><topic>Power system interconnection</topic><topic>Shift registers</topic><topic>System-on-a-chip</topic><topic>Throughput</topic><topic>Transmitters</topic><toplevel>online_resources</toplevel><creatorcontrib>Dobkin, R.</creatorcontrib><creatorcontrib>Perelman, Y.</creatorcontrib><creatorcontrib>Liran, T.</creatorcontrib><creatorcontrib>Ginosar, R.</creatorcontrib><creatorcontrib>Kolodny, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dobkin, R.</au><au>Perelman, Y.</au><au>Liran, T.</au><au>Ginosar, R.</au><au>Kolodny, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link</atitle><btitle>13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)</btitle><stitle>ASYNC</stitle><date>2007-03</date><risdate>2007</risdate><spage>3</spage><epage>14</epage><pages>3-14</pages><issn>1522-8681</issn><isbn>076952771X</isbn><isbn>9780769527710</isbn><abstract>A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.</abstract><pub>IEEE</pub><doi>10.1109/ASYNC.2007.20</doi><tpages>12</tpages><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISSN: 1522-8681
ispartof	13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007, p.3-14
issn	1522-8681
language	eng
recordid	cdi_ieee_primary_4137028
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Clocks Costs Delay Driver circuits Integrated circuit interconnections Power system interconnection Shift registers System-on-a-chip Throughput Transmitters
title	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T05%3A03%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=High%20Rate%20Wave-pipelined%20Asynchronous%20On-chip%20Bit-serial%20Data%20Link&rft.btitle=13th%20IEEE%20International%20Symposium%20on%20Asynchronous%20Circuits%20and%20Systems%20(ASYNC'07)&rft.au=Dobkin,%20R.&rft.date=2007-03&rft.spage=3&rft.epage=14&rft.pages=3-14&rft.issn=1522-8681&rft.isbn=076952771X&rft.isbn_list=9780769527710&rft_id=info:doi/10.1109/ASYNC.2007.20&rft_dat=%3Cieee_6IE%3E4137028%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4137028&rfr_iscdi=true